Logic design has become more formalized over the last several years due to the increasing complexity of the circuits being designed. A result has been an increased need for logic simulation at the level of the design by using a hardware description language to express the design. This need for simulation capability has put a great emphasis on execution speed of HDL simulators. This lecture describes the need for large amounts of simulation and techniques which can be used to implement a fast simulator. Examples are taken from Chronologic Simulation's VCS Verilog compiler."
University Video Communications: Distinguished Lectures