TitleSilicon Graphics TFP micro-supercomputer chipset
PublisherUniversity Video Communications
Copyright HolderComputer History Museum
DescriptionFrom University Video Communications' catalog:
"The Silicon Graphics TFP microprocessor is a superscalar implementation of the MIPS instruction set architecture targeted at floating point intensive applications. Highlights include a four-issue instruction unit with branch prediction, a split-level interleaved cache that sustains two loads or stores per cycle, and a 300 mflops floating point unit."