Artifact Details

Title

Hoerni patent notebook (#3)

Catalog Number

102722910

Type

Text

Date

1957-11-07-1960-12-22

Author

Hoerni, Jean A.

Biographical Notes

Born in Switzerland in 1924, Jean Amédée Hoerni earned Ph.D.s in physics at the Universities of Geneva and Cambridge. After moving to the U.S. he worked as a research fellow with Linus Pauling at the California Institute of Technology. He joined Shockley Semiconductor Laboratory in 1956 and left in September 1957 to co-found Fairchild Semiconductor Corporation with seven other dissidents. At Fairchild, Hoerni conceived the planar silicon transistor in December 1957 and successfully developed it in early 1959. His planar processing technique revolutionized semiconductor manufacturing and was adopted worldwide. It also led to the invention of the monolithic integrated circuit by R. Noyce at Fairchild. Hoerni left Fairchild with J. Last in early 1961 to found the Amelco divison of Teledyne, Inc., to manufacture integrated circuits. He left Teledyne in 1963 for Union Carbide, heading a research unit. In 1967 he established Intersil (short for International Silicon) with mainly European investors, producing MOS transistors and integrated circuits for calculators and watches. He founded several other companies, including Telmos to make high-voltage MOS devices. Hoerni received numerous industry awards. He is most widely known outside industry circles for his endowment of the Central Asia Institute to build schools in remote areas of Pakistan and Afghanistan. He died in 1997.

Publisher

Fairchild Semiconductor Corporation

Identifying Numbers

Document number 3

Extent

Approximately 22 dated entries over 30 pages.

Dimensions

12 x 10 inches

Description

This volume contains a mix of brief notes on the status of experimental wafers together with extended disclosures of process and design ideas that were used as the basis for patent filings. Specific entries include: "Method of protecting exposed p-n junctions at the surface of silicon transistors by oxide masking techniques" (pp. 3-4) this was his first expression of the planar process – U.S. patent 3025589; "Effect of gold-doping on lifetimes in transistors" (pp. 7-11) – U.S. patent 3108914; “Use of selective control on electron and hole lifetimes in semiconductor devices” (pp. 12-15) – U.S. patent 3184347; “PNP planar transistors” (pp. 17-18); “On the application of the Merck growing technique to device structures;” “Observations on the impact and applications of epitaxial films” (pp. 23-24); “Logic using unipolar transistors” proposes a practical method of implementing the ideas of Walmark at RCA (pp. 26–28).

Patents

The author is named as inventor on 4 U.S. patents; all 4 patents are assigned to Fairchild:

U.S. patent 3025589, “Method of manufacturing semiconductor devices.” Filed 1959-05-01. Issued 1962-03-20.

U.S. patent 3064167, “Semiconductor device.” Filed 1959-05-01. Issued 1962-11-13.

U.S. patent 3108914, “Transistor manufacturing process.” Filed 1959-06-30. Issued 1963-10-29.

U.S. patent 3184347, “Selective control of electron and hole lifetimes in transistors.” Filed 1962-07-19. Issued 1965-05-18.

Category

Notebooks

Collection Title

Fairchild Semiconductor notebooks and technical papers

Publications

The author contributed to the following conference paper during his service at Fairchild:

Hoerni, J. A., Planar silicon diodes and transistors. 1960 International Electron Devices Meeting, vol. 6 (1960): 50.
Reprinted as Fairchild Semiconductor technical paper TP-14, (1961).

Credit

Gift of Texas Instruments Incorporated

Lot Number

X6464.2012