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Details

Catalog Number

102722944

Title

Chou laboratory notebook (Lateral PNP III)

Type

Text

Date

1969-03-24-1969-07-14

Author

Chou, Sunlin

Biographical Notes

Sunlin Chou was born in Singapore and received B.S., M.S., and E.E. degrees from MIT in 1966, 1967, and 1968 respectively, all in electrical engineering. He joined Fairchild in 1968 where he worked on the development of a lateral PNP transistor and was involved in the set-up and operation of an ion implantation system while also earning a Ph.D. from Stanford University (1971). He moved to Intel Corporation in 1971, and worked on device modeling, memory design, and process development projects, before assuming responsibility for Intel’s DRAM process technology development effort. He was senior vice president and general manager of Intel’s Technology and Manufacturing Group when he retired in 2005. He was awarded the IEEE Robert Noyce Award in 2013.

Publisher

Fairchild Semiconductor

Identifying Numbers

Document number III.

Extent

Approximately 90 dated entries over 196 pages.

Dimensions

10 x 8 inches

Description

This is Volume III in a series of notebooks recording the processing of wafer runs fabricated in the development of a lateral PNP transistor for use in IC designs. It contains a day-by-day, minute-by-minute log of activity, including the results of a visual microscope inspection of the condition of the surface and notes on additional processing to be applied to the material

Category

Notebooks

Collection Title

Fairchild Semiconductor notebooks and technical papers

Publications

The author contributed to the following R&D Technical Reports (TR) and papers in professional publications during his service at Fairchild:

TR430 An investigation of lateral transistors I. DC characteristics [1968-9-10-06].

TR446 On the measurement of recombination currents in epitaxial base transistors [1969-12-12].

TR464 A study of diffused layers of arsenic and antimony in silicon using the ion scattering technique [1970-05-22].

TR504 An investigation of lateral transistors II - small signal characteristics [1971-03-26].

*S. Chou. An investigation of lateral transistors - D.C. characteristics [1971]. Solid-State Electronics, vol. 14, iss. 9 (1971-09): 811–826.

*S. Chou. Small-signal characteristics of lateral transistors [1972]. Solid-State Electronics, vol. 15, iss. 1 (1972-01): 27–38.

*S. Chou, L. A. Davidson, and J. F. Gibbons. A study of diffused layers of arsenic and antimony in silicon using the ion-scattering technique. Applied Physics Letters, vol. 17, iss. 1 (1970-07): 23.

* This paper is included in a three volume bound set of “Fairchild Research Published Technical Papers” assembled by Bruce Deal in 1988 (copy in the CHM Fairchild collection).

Credit

Gift of Texas Instruments Incorporated

Lot Number

X6464.2012