TitleForsythe patent notebook (#551)
AuthorForsythe, Donald Dave (David)
Biographical NotesDonald David (Dave) Forsythe joined Fairchild circa 1966 as a Senior Engineer in the Technology Development group reporting to C. Plough where he worked on printing techniques for hybrid ICs. In 1968 he reported to L. Vadasz in the MOS Circuit and Device Technology group. During this time he worked with T. Klein, D. Frohman and F. Faggin on MOS reliability projects. In 1980 he was employed at Synertek and after 1990 at National Semiconductor.
ExtentApproximately 10 dated entries over 39 pages.
Dimensions12 x 10 inches
DescriptionThe first 27 pages describe the development of printing equipment and processes for hybrid ICs. Other entries include; MNOS memory array random access (pp. 27-37); and two-level P-channel logic and ion-implant level shifter (pp. 38-39).
PatentsThe author was named as inventor of at least 3 U.S. Patents. None of these patents were assigned to Fairchild.
Collection TitleFairchild Semiconductor notebooks and technical papers
PublicationsThe author contributed to the following R&D Technical Reports (TR) and papers in professional publications during his service at Fairchild:
TR365 Anomalous link current (1968-11-01).
TR489 Room temperature instabilities observed on silicon-gate devices (1970-10-30).
Faggin, F., Forsythe, D. D. and Klein, T. Room temperature instabilities observed on silicon gate devices. 1970 8th Annual Reliability Physics Symposium (1970): 35-41.
*Forsythe, D.D. Surface-charge induced failures observed on MOS integrated circuits.
Microelectronics Reliability, vol. 8, iss. 4, (1969-11): 339-340.
Frohman-Bentchkowsky, D. and Forsythe, D.D. Reliability of MNOS integrated circuits. 1969 International Electron Devices Meeting, vol. 15 (1969): 48.
*Paper included in the set of three bound volumes of “Fairchild Research Published Technical Papers” assembled by Bruce Deal in 1988.