Lionel Estes Kattner (1930 – 2011) received a degree in chemistry, physics and math from Southwestern University, located in Georgetown, Texas in 1951. After graduation he worked at the Hanford, Washington plant on the production of plutonium for nuclear weapons and later served as a nuclear officer in the United States Navy. In 1958 he joined Texas Instruments in Dallas as a product engineer on a germanium mesa transistor product line. In 1959 Kattner was recruited into Jay Last’s microelectronics group at Fairchild Semiconductor where he worked closely with I. Haas on the fabrication of Micrologic, the first planar integrated circuit family. With three other Fairchild employees, he co-founded Signetics Corporation in 1961. He resigned from Signetics in 1967 and spent two years at Amelco Semiconductor. From 1969 until his retirement Kattner was involved with various projects and startups, including real estate development, computers, computerized mapping, microwave communications and fiber optics.
Approximately 14 dated entries over 84 pages.
10 x 8 inches
Page 1 includes schematics and formulae on tunnel diode operation. The balance of the volume contains working notes on process steps and calculations related to diffusion and etching of wafer runs used to fabricate the Micrologic flip flop, the first working planar IC, in 1960-05. Each wafer run is designated FF1XX from FF100 on 1960-03-04 through FF119. An entry on FF105 dated 1960-05-26 describes the process used to make the first run to yield a working device (that according to Fok (126) was tested on 1960-05-12). The first calculations related to the methyl borate diffusion process successfully used to make electrically (junction) isolated devices appear on 1960-09-27.
The author is named as inventor on 1 U.S patent. This patent is not assigned to Fairchild.
Fairchild Semiconductor notebooks and technical papers