TitleMoore patent notebook (LN #2)
AuthorMoore, Gordon E.
Biographical NotesGordon Earle Moore was born in San Francisco, California, in 1929. He earned a B.S. in Chemistry from the University of California at Berkeley in 1950 and a Ph.D. in Physical Chemistry from the California Institute of Technology in 1954. He joined Shockley Semiconductor Laboratory in 1956 and left to co-found Fairchild Semiconductor in 1957. He succeeded Robert Noyce as Director of the Research and Development Laboratory in 1959 and left to co-found Intel in 1968. He served initially as Executive Vice President, became President and Chief Executive Officer in 1975 and held that post until elected Chairman and Chief Executive Officer in 1979. He remained CEO until 1987 and was named Chairman Emeritus in 1997. Moore is widely known for “Moore’s Law”. In an article "Cramming More Components onto Integrated Circuits," published in Electronics magazine in 1965, he predicted that the number of transistors the industry would be able to place on a computer chip would double every year. In 1975, he updated his prediction to once every two years. Originally intended to stimulate customer interest in using more complex Fairchild ICs in their new system designs, it has evolved into a guiding principle for the industry to deliver ever-more-powerful semiconductor chips at proportionate decreases in cost. Moore and his wife established the Gordon and Betty Moore Foundation in 2000 to fund projects aimed at improving the quality of life for future generations. He is a director of Gilead Sciences Inc., a member of the National Academy of Engineering and a Fellow of the IEEE. Moore also serves on the Board of Trustees of the California Institute of Technology. He received the National Medal of Technology from President George Bush in 1990.
ExtentApproximately 90 dated entries over 142 pages.
Dimensions12 x 10 inches
DescriptionThis volume contains notes relating to R&D product reviews and miscellaneous meetings to discuss customer opportunities (Autonetics, NSA, etc.), Step & repeat ramera issues, and specific production and research problems. Most meetings include an attendee list. Many internal memos and reports related to the topics under discussion are stapled or loosely inserted into the appropriate meeting pages. A complete typed R&D project review “Table of Contents” listing is inserted into the front of the volume. Page 142 has a useful cross-reference guide to the Job Numbers assigned to each product area. Approximately 26 unique product categories are grouped under the following headings: “Transistors & Diodes” (12), “Peizo resistor” (1), “Misc. Devices” (10) – includes “Data Storage”, “Microwave”, “SCT”, “Tunnel Diode”, “Phototransistor”, “FET”, “Ferromagnetics” and “Microcircuitry” (3).
PatentsThe author is named as inventor on 6 U.S patents, including 4 patents assigned to Fairchild:
U.S. patent 3184657, “Nested region transistor configuration.” Filed 1962-01-05. Issued 1965-05-18.
U.S. patent 3212162, “Fabricating semiconductor devices.” Filed 1962-01-05. Issued 1965-10-19.
U.S. patent 3271640, “Semiconductor tetrode.” Filed 1962-10-11. Issued 1966-09-06.
U.S. patent 3108359, “Method for fabricating transistors.” Filed 1959-01-30. Issued 1963-10-29.
Collection TitleFairchild Semiconductor notebooks and technical papers
PublicationsThe author contributed to the following publications during his service at Fairchild:
Allison, D. F., Baker, O. and Moore, G. E., KMC silicon planar transistors. 1961 International Electron Devices Meeting, vol. 7 (1961): 18.
Moore, G., Cramming more components onto integrated circuits. Electronics Magazine, vol. 38, no. 8 (1965-04-19).
Moore, G., “Microelectronics.” chap. 5 in Semiconductor Integrated Circuits, ed. Edward Keonjian. McGraw-Hill, 1963.
Moore, G. E., The MOS transistor as an individual device and in integrated arrays. Part 5 of the IEEE International Convention Record, (1965): 44-52.
Moore, G. E., Trends in silicon device technology. 1968 International Electron Devices Meeting, vol. 14 (1968): 12.