TitleSander patent notebook (#1290)
AuthorSander, Wendell B.
Biographical NotesWendell B. Sander received a Ph.D. in Electronics from Iowa State University. He joined Fairchild circa 1964 where he pioneered the design of gate arrays and semiconductor memory, including the first major computer design to use semiconductors in a main memory application (Illiac IV). In 1968 he was listed on the R & D Professional Staff - Org, Chart as head of the Complex Array Engineering section of the Digital Integrated Electronics Deptartment reporting to R. Seeds. He joined Apple Computer in 1977 as the 16th employee where he designed Apple II peripherals and the Apple III computer. In 1985 he founded a contract design engineering company, The Engineering Department, Inc. Projects included the technology used to found Echelon Corporation. In 1987 he co-founded Mpulse Microwave, a microwave and RF diode manufacturer, as the primary investor. In 1990 he joined General Magic, Inc. as Fellow providing new technology guidance in the development of PDAs. In 1992 he co-founded ChipScale, Inc. to exploit a new semiconductor packaging concept.
ExtentApproximately 10 dated entries over 23 pages.
Dimensions12 x 10 inches
DescriptionThis volume contains semiconductor device structures and circuit designs for memory cell applications, including a two-dimensional (p. 16) and suggested applications.
PatentsThe author is named as inventor on over 30 U.S patents. 4 of these are assigned to Fairchild:
U.S. patent 3654610, "Use of faulty storage circuits by position coding." Filed 1970-09-28. Issued 1972-04-04.
U.S. patent 3859518, "CCD light change monitor." Filed 1974-01-07. Issued 1975-01-07.
U.S. patent 3898483, "Bipolar memory circuit." Filed 1973-10-18. Issued 1973-10-18.
U.S. patent 3530443, "MOS gated resistor memory cell." Filed 1968-11-27. Issued 1970-09-22.
Collection TitleFairchild Semiconductor notebooks and technical papers
PublicationsThe author contributed to the following papers in professional publications during his service at Fairchild:
Greene, F.S. and Sander, W.B. Address selection by combinatorial decoding of semiconductor memory arrays. IEEE Journal of Solid-State Circuits, vol. 4, iss. 5 (1969): 295 – 296.
Quinn, P., Early, J., Sander, W. and Longo, T. A 16K ×1 I3L dynamic RAM. 1978 IEEE International Solid-State Circuits Conference: Digest of Technical Papers. vol. XXI (1978): 154-155.
Rice, R., Sander, W.B., Jr. and Greene, F.S. Design considerations leading to the ILLIAC IV LSI process element memories. IEEE Journal of Solid-State Circuits, vol. 5, iss. 5 (1970): 174-181.
Sander, W., Early, J. and Longo, T. A 4096 × 1 (I3L) bipolar dynamic RAM . 1976 IEEE International Solid-State Circuits Conference: Digest of Technical Papers, vol. XIX (1976): 182-183.
Vadasz, L., Nevala, R., Sander, W. and Seeds, R. A systematic engineering approach to complex arrays. 1966 IEEE International Solid-State Circuits Conference: Digest of Technical Papers. vol. IX (1966): 120 – 121.