Title
Vadász patent notebook (#416)Catalog Number
102723045Type
DocumentDescription
The author begins with a humorous note bidding goodbye to his first notebook (#393). This volume continues the prior MOS IC design work. The initial entries examine systematic layout practices for complex circuits (pp. 2–11 and pp. 18-25); comments on mask taping (p. 41); 4-phase logic circuit measurements (pp. 54-62); dynamic shift register design (pp. 73-75); MOS yield information (various pages between 76 and 94); input gate protection (pp. 95-98); parasitc MOS problem (pp. 104-110); MOS with thick oxide (pp. 114-116); Schottky diodes on MOS ICs (pp. 129-131); and differential Qss technology (pp.132-134).Date
1965-02-05-1968-03-18Author
Vadász, Leslie L.Biographical Notes
Leslie L. Vadász was born in Budapest, Hungary, in 1936. He received a B.S.E.E. from McGill University in 1961 and completed the Harvard University Advanced Management Program in 1990. He moved to the United States in 1961 where he joined Transitron Corporation, located in Wakefield, Massachusetts. He served on the technical staff of Fairchild from 1964 to 1968 where he was a Senior Engineer in the Circuits and Development Technology Section reporting to R. Foglesong in 1966. In 1968 he was head of the MOS Circuit and Device Technology Section reporting to R. Seeds, Manager of the Digital Integrated Electronics Department where he worked on silicon-gate MOS technology. He joined Intel as the fourth employee in 1968 and remained with the company until retiring in 2003. His roles at Intel included Director of Engineering, General Manager, Microcomputer Components Division, Executive Vice President and member of the Board of Directors.Publisher
Fairchild SemiconductorIdentifying Numbers
| Document number | 416 |
Extent
Approximately 42 dated entries over 137 pages.Dimensions
12 x 10 inchesPatents
The author is named as inventor on 1 U.S patent. It was not assigned to Fairchild.Category
NotebooksCollection Title
Fairchild Semiconductor notebooks and technical papersPublications
The author contributed to the following R&D Technical Reports (TR) and papers in professional publications during his service at Fairchild:TR228 The use of MOS structure for the design of high value resistors in monolithic integrated circuits (1965-10-20).
TR260 Temperature dependence of the MOS transistor characteristics below saturation (1966-08-05) .
TR299 MOS device characterization (1967-05-31).
Chopra, A. and Vadasz, L., Silicon MOS field effect transistors using impurity redistribution during oxidation. Proceedings of the IEEE, vol. 52, iss. 8 (1964): 985-986.
Faggin, F., Klein, T. and Vadasz, L., Insulated gate field effect transistor integrated circuits with silicon gates. 1968 International Electron Devices Meeting, vol. 14 (1968): 22.
Frohman-Bentchkowsky, D. and Vadasz, L., Computer-aided design and characterization of digital MOS integrated circuits, IEEE Journal of Solid-State Circuits, vol. 4, iss. 2 (1969): 57-64.
Frohman-Bentchkowsky, D. and Vadasz, L., Computer-aided design and characterization of MOS integrated circuits. 1968 IEEE International Solid-State Circuits Conference: Digest of Technical Papers, vol. XI (1968): 68-69.
Frohman-Bentchkowsky, D. and Vadasz, L., DC analysis of an MOS source follower. IEEE Journal of Solid-State Circuits, Vol. 3, Iss. 3 (1968): 306-307.
Root, C. D. and Vadasz, L., Design calculations for MOS field effect transistors. IEEE Transactions on Electron Devices, vol. 11, iss. 6 (1964): 294-299.
Vadasz, L., MOS resistor — a monolithic approach to high value resistance. 1965 International Electron Devices Meeting, vol. 11 (1965): 37.
Vadasz, L., The use of MOS structure for the design of high value resistors in monolithic integrated circuits. IEEE Transactions on Electron Devices, vol. 13, iss. 5 (1966): 459-465.
Vadasz, L. and Grove, A. S., Temperature dependence of MOS transistor characteristics below saturation, IEEE Transactions on Electron Devices, vol. 13, iss. 12 (1966): 863-866.
Vadasz, L., Nevala, R., Sander, W. and Seeds, R., A systematic engineering approach to complex arrays. 1966 IEEE International Solid-State Circuits Conference: Digest of Technical Papers. vol. IX (1966): 120 – 121.