Artifact Details

Title

Angell patent notebook (#287)

Catalog Number

102723947

Type

Text

Date

1963-03-21-1966-10-11

Author

Angell, James

Biographical Notes

James Browne Angell was born on Staten Island, New York., in 1924. He received a B.S. in 1946, M.S. also in 1946 and Ph.D. in 1952 in electrical engineering from the Massachusetts Institute of Technology and from 1946 to 1951 he studied noise in tracking radars at MIT's Research Laboratory of Electronics. He worked for Philco on circuit applications and evaluation of transistors and other solid-state devices for 9 years where he met Fairchild and Intel co-founder Robert Noyce. He joined Stanford's Department of Electrical Engineering in 1960 and became a full professor in 1962. From 1963 through 1973 he consulted with the Fairchild Semiconductor R&D department in Palo Alto. He directed the Stanford Solid-State Industrial Affiliates program from 1964 to 1970. He retired in 1991 and died in 2006. Angell recommended Ted Hoff to Intel, where he became employee number 12. Hoff designed the architecture for Intel’s first microprocessor. Angell appeared with Harry Sello in Fairchild’s 1967 Briefing on Integrated Circuits video infomercial on PBS.

Publisher

Fairchild Semiconductor

Identifying Numbers

Document number 287

Extent

Approximately 77 dated entries over 149 pages.

Dimensions

12 x 10 inches

Description

This volume describes projects for Rex Rice and others related to magnetic and semiconductor memory storage devices. Extensive manual calculations, tables and charts investigating optimum yield and cost for various approaches to enhancing device yield through the addition of redundant storage elements. Significant entries include: design considerations for using drum memory in combination with TV (CRT) readout displays (pp. 1-32); factors to be considered in building “Bigger integrated circuits” of 50 to 500 transistor complexity (p. 32); notes that Jack Schmidt is making a 4 bit x 16 word RAM (p. 35); considerations for the use of redundancy to improve yield of 16x16 memory chips and analysis of relative costs (p. 36); buffer register design considerations for yield and speed (pp. 106-114); yield analysis for 4x4 DWSA array (pp. 118-149). This book includes a loose 4 page outline on “Improving yield of Large Scale ICs via modest redundancy” to a 64-bit RAM and a Four Stage Register. This resulted in the Fairchild R&D Technical Report TR 245 (below).

This is 1 of 2 books issued to Angell. The other book is Angell (616).

Patents

The author is named as inventor on 2 patents assigned to Fairchild:

U.S. patent 3325787, “Trainable system.” Filed 1964-10-19. Issued 1967-06-13.

U.S. patent 3530443, “MOS gated resistor memory cell.” Filed 1968-11-27. Issued 1970-09-22.

Category

Notebooks

Collection Title

Fairchild Semiconductor notebooks and technical papers

Publications

The author contributed to the following R&D Technical Reports (TR) and papers in professional publications during his service at Fairchild:

TR 245 Improving yield of integrated arrays via redundancy (1966-03-30).

Angell, J. B., The need and means for self-repairing circuits. Proceedings of the IEEE, vol. 51 , iss. 3 (1963): 536.

Linvill, J. G., Angell, J. B. and Pritchard, R. L., Integrated electronics vs electrical engineering education . Proceedings of the IEEE, vol. 52, iss. 12 (1964): 1425-1429.

Pritchard, R. L., Angell, J. B., Adler, R. B., Early, J. M. and Webster, W. M., Transistor Internal Parameters for Small-Signal Representation. Proceedings of the IRE, vol. 49, iss. 4 (1961): 725-738.

Tammaru, E. and Angell, J. B., Redundancy for LSI Yield Enhancement. IEEE Journal of Solid-State Circuits, vol. 2, iss. 4 (1967): 172-182.

Thornton, C. G. and Angell, J. B., Technology of Micro-Alloy Diffused Transistors. Proceedings of the IRE, vol. 46, iss. 6 (1958): 1166-1176.

Widrow, B., Pierce, W. H. and Angell, J. B., Birth, Life, and Death in Microelectronic Systems . IRE Transactions on Military Electronics, vol. MIL-5, iss. 3 (1961): 191-201.

Williams, M. J. Y. and Angell, J. B., Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic. IEEE Transactions on Computers, vol. C-22, iss. 1 (1973): 46-60.

Credit

Gift of Texas Instruments Incorporated

Lot Number

X6464.2012