TitleLehrer patent notebook (#484)
AuthorLehrer, Bill (William) I.
Biographical NotesWilliam (Bill) I. Lehrer joined Fairchild R&D Lab circa 1963 where he initially worked on thin film metal deposition process technology under Heinz Ruegg. In 1966 he was listed as a Senior Engineer in the Exploratory Devices section managed by C. Bittmann. He appears to have left Fairchild in 1967 and worked independently with former Fairchild colleague Herbert Kroemer with whom he is named a co-inventor of U.S. patent # 3488542 “Light emitting heterojunction semiconductor devices” (Filed 1967-09-01. Issued 1970-01-06). Kroemer received the 2000 Nobel Prize in Physics for his work on heterojunction devices. Lehrer returned to Fairchild in the 1970s as a Member of the Technical Staff in the Integrated Circuits R & D department and remained with the company through its acquisition by National Semiconductor in 1987. He was one of Fairchild’s most prolific inventors; over 20 U.S. patents were issued under his name. Additional patents were granted in Europe.
ExtentApproximately 95 dated entries over 115 pages.
Dimensions12 x 10 inches
DescriptionDescribes process steps to accomplish a variety of silicon and GaAs microwave frequency device structures, interconnections, and packaging methods, accompanied by numerous cross-section sketches, Polaroid microphotographs, and hand plotted graphs. Page 3 (1966-02-15) discloses the technique of U.S. patent 3498833 (below). Page 50 (1966-07-28) begins disclosures related to the GaAs film vacuum deposition method of U.S. patent 3476593. Page 104 (1967-12-13) discloses the Suppressor Plate geometry of U.S. patent 3538371.
This is one of 4 books authored by Lehrer. The other three are designated 306, 1198 and 84-3042.
PatentsThe author is named as inventor on many U.S patents, including 20 patents assigned to Fairchild:
U.S. patent 3498833, “Double masking technique for integrated circuit.” Filed 1966-07-08. Issued 1970-03-03.
U.S. patent 3475210, “Laminated passivating structure.” Filed 1966-05-06. Issued 1969-10-28.
U.S. patent 3476593, “Method of forming gallium arsenide films by vacuum deposition techniques.” Filed 1967-01-24. Issued 1969-11-04.
U.S. patent 3788723, “Method of preparing cavity envelopes.” Filed 1972-04-24. Issued 1974 .
U.S. patent 3538371, “Glow discharge display device with suppressor plate.” Filed 1968-06-04. Issued 1970-11-03.
U.S. patent 4442449, “Binary germanium-silicon interconnect and electrode structure.” Filed 1981-03-16. Issued 1984-04-10.
U.S. patent 4490737, “Smooth glass insulating film over interconnects on an integrated circuit.” Filed 1982-03-26. Issued 1984-12-25.
U.S. patent 4704342, “Photomask having a patterned carbon light-blocking coating.” Filed 1985-04-02. Issued 1987-11-03.
U.S. patent 4431900, “Laser induced flow Ge-O based materials.” Filed 1982-01-15. Issued 1984-02-14.
U.S. patent 4420365, “Formation of patterned film over semiconductor structure.” Filed 1983-03-14. Issued 1983-12-13.
U.S. patent 4398335, “Multilayer metal silicide interconnections for integrated circuits.” Filed 1980-12-09. Issued 1983-08-16.
U.S. patent 4619839, “Method of forming a dielectric layer on a semiconductor device.” Filed 1984-12-12. Issued 1986-10-28.
U.S. patent 4619844, “Method and apparatus for low pressure chemical vapor deposition.” Filed 1985-01-22. Issued 1986-10-28.
U.S. patent 4630343, “Product for making isolated semiconductor structure.” Filed 1985-09-06. Issued 1986-12-23).
U.S. patent 4267012, “Process for patterning metal connections on a semiconductor structure.” Filed 1979-04-30. Issued 1981-05-12.
U.S. patent 4359490, “Method for LPCVD co-deposition of metal and silicon to form metal silicide.” Filed 1981-07-13. Issued 1982-11-16.
U.S. patent 4727048, “Process for making isolated semiconductor structure.” Filed 1986-10-02. Issued 1988-02-23.
U.S. patent 4972251, “Multilayer glass passivation structure and method for forming the same.” Filed 1985-08-14. Issued 1990-11-20.
U.S. patent 4935095, “Germanosilicate spin-on glasses.” Filed 1985-06-21. Issued 1990-06-19.
U.S. patent 4654269, “Stress relieved intermediate insulating layer for multilayer metallization.” Filed 1985-06-21. Issued 1987-03-31.
Collection TitleFairchild Semiconductor notebooks and technical papers
PublicationsThe author contributed to the following R&D Technical Reports (TR) and papers in professional publications during his service at Fairchild:
TR256 Application of the calcium fluoride lifting technique to planar structures (1966-08-25).
Hooper, W.W. and Lehrer, W.I. An epitaxial GaAs field-effect transistor. Proceedings of the IEEE, vol. 55, iss. 7 (1967): 1237-1238.