Artifact Details

Title

Moore patent notebook (L.N.#3)

Catalog Number

102723965

Type

Text

Date

1962-11-15-1963-06-06

Author

Moore, Gordon E.

Biographical Notes

Gordon Earle Moore was born in San Francisco, California, in 1929. He earned a B.S. in Chemistry from the University of California at Berkeley in 1950 and a Ph.D. in Physical Chemistry from the California Institute of Technology in 1954. He joined Shockley Semiconductor Laboratory in 1956 and left to co-found Fairchild Semiconductor in 1957. He succeeded Robert Noyce as Director of the Research and Development Laboratory in 1959 and left to co-found Intel in 1968. He served initially as Executive Vice President, became President and Chief Executive Officer in 1975 and held that post until elected Chairman and Chief Executive Officer in 1979. He remained CEO until 1987 and was named Chairman Emeritus in 1997. Moore is widely known for “Moore’s Law”. In an article "Cramming More Components onto Integrated Circuits," published in Electronics magazine in 1965, he predicted that the number of transistors the industry would be able to place on a computer chip would double every year. In 1975, he updated his prediction to once every two years. Originally intended to stimulate customer interest in using more complex Fairchild ICs in their new system designs, it has evolved into a guiding principle for the industry to deliver ever-more-powerful semiconductor chips at proportionate decreases in cost. Moore and his wife established the Gordon and Betty Moore Foundation in 2000 to fund projects aimed at improving the quality of life for future generations. He is a director of Gilead Sciences Inc., a member of the National Academy of Engineering and a Fellow of the IEEE. Moore also serves on the Board of Trustees of the California Institute of Technology. He received the National Medal of Technology from President George Bush in 1990.

Publisher

Fairchild Semiconductor

Identifying Numbers

Document number L.N.#3

Extent

Approximately 90 dated entries over 147 pages.

Dimensions

12 x 10 inches

Description

As with earlier books, this volume contains notes made in preparation for and during routine meetings (staff, R&D project status, etc.) and meetings to discuss customer opportunities and specific production and research problems. Most meetings include an attendee list. Many internal memos and reports related to the topics under discussion are stapled or loosely inserted into the appropriate meeting pages. Key topics covered include epitaxial process status, project ROBE (Resistive Oxidative Backside Etched), mask making technology, and thin film resistors. Pages 138-139 records the first discussions of work by Deal, Grove, and Sah on the silicon to silicon dioxide interface “channel phenomena” that dominated the MOS business in later years. He notes frustration with the lack of direction concerning future IC products – “As far as I can see this whole area of digital integrated circuitry is badly up in the air.”

This is one of 5 notebooks by Moore in the collection. The other 4 books by Moore are designated 6, LN#1, LN#2, and LN#4. Note that volumes LN#1 and LN#2 are labeled in reverse chronological order; LN#2 covers an earlier period than LN#1. Also there is gap of 2 years between LN#3 (ends 1963) and LN#4 (begins 1965).

Patents

The author is named as inventor on 6 U.S patents, including 4 patents assigned to Fairchild:

U.S. patent 3184657, “Nested region transistor configuration.” Filed 1962-01-05. Issued 1965-05-18.

U.S. patent 3212162, “Fabricating semiconductor devices.” Filed 1962-01-05. Issued 1965-10-19.

U.S. patent 3271640, “Semiconductor tetrode.” Filed 1962-10-11. Issued 1966-09-06.

U.S. patent 3108359, “Method for fabricating transistors.” Filed 1959-01-30. Issued 1963-10-29.

Category

Notebooks

Collection Title

Fairchild Semiconductor notebooks and technical papers

Publications

The author contributed to the following publications during his service at Fairchild:

Allison, D. F., Baker, O. and Moore, G. E., KMC silicon planar transistors. 1961 International Electron Devices Meeting, vol. 7 (1961): 18.

Moore, G., Cramming more components onto integrated circuits. Electronics Magazine, vol. 38, no. 8 (1965-04-19).

Moore, G., “Microelectronics.” chap. 5 in Semiconductor Integrated Circuits, ed. Edward Keonjian. McGraw-Hill, 1963.

Moore, G. E., The MOS transistor as an individual device and in integrated arrays. Part 5 of the IEEE International Convention Record, (1965): 44-52.

Moore, G. E., Trends in silicon device technology. 1968 International Electron Devices Meeting, vol. 14 (1968): 12.

Credit

Gift of Texas Instruments Incorporated

Lot Number

X6464.2012