Artifact Details

Title

Submicron CMOS technology scaling issues

Catalog Number

102724527

Type

Moving image

Date

1989-02-03

Credits

Haken, Roger A.

Publisher

University Video Communications

Duration

00:54:20

Format

Betacam SP

Copyright Holder

Computer History Museum

Description

From University Video Communications' catalog:

"In VLSI design, there are important technical constraints to understand when scaling CMOS into the submicron regime. In this tutorial, Roger Haken discusses the scaling limitations of 2 micron CMOS process technology, crossing the 1 micron technology discontinuity (MOS transistor design, low resistivity gates and diffusions, isolation technology, latch-up prevention, multilevel interconnect [global and local]), and the application of scaled technologies to a submicron CMOS process."

Category

Lecture

Collection Title

University Video Communications lectures

Series Title

Distinguished Lecture Series : Microelectronics

Credit

Gift of University Video Communications

Lot Number

X6636.2013