TitleSubmicron CMOS technology scaling issues
CreditsHaken, Roger A.
PublisherUniversity Video Communications
Copyright HolderComputer History Museum
DescriptionFrom University Video Communications' catalog:
"In VLSI design, there are important technical constraints to understand when scaling CMOS into the submicron regime. In this tutorial, Roger Haken discusses the scaling limitations of 2 micron CMOS process technology, crossing the 1 micron technology discontinuity (MOS transistor design, low resistivity gates and diffusions, isolation technology, latch-up prevention, multilevel interconnect [global and local]), and the application of scaled technologies to a submicron CMOS process."