Title
Western Research Laboratory research reports 91/3-95/4Catalog Number
102737736Type
DocumentDescription
This box contains the following technical reports, filed in the same order as this list:Analysis of power supply networks in VLSI circuits
TurboChannel T1 adapter
Procedure merging with instruction caches
Don’t fidget with widgets, draw!
Pool boiling on small heat dissipating elements in water at subatmospheric pressure
Incremental, generational mostly-copying garbage collection in uncooperative environments
Interleaved fin thermal connectors for multichip modules
Experience with a software-defined machine architecture
Network locality at the scale of processes
Packaging a 150 W bipolar ECL microprocessor
Observing TCP dynamics in real networks
Systems for late code modification
Piecewise linear models for switch-level simulation
Practical system for intermodule code optimization at link-time
Smart frame buffer
Unreachable procedures in object-oriented programming
Limits of instruction-level parallelism
Fluoroelastomer pressure pad design for microelectronic applications
300MHz 115W 32b bipolar ECL microprocessor
Link-time optimization of address calculation on a 64-bit architecture
ATOM : a system for building customized program analysis tools
Complexity/performance tradoffs with non-blocking loads
Better update policy
Boolean matching for full-custom ECL gates
Software methods for system address tracing : implementation and validation by J. Bradley Chen, David W. Wall, and Anita Borg
Performance implications of multiple pointer size by Jeffrey C. Mogul, Joel F. Bartlett, Robert N. Mayo, and Amitabh Srivastava
How useful are non-blocking loads stream buffers and speculative execution in multiple issue processors by Keith I. Farkas, Norman P. Jouppi, and Paul Chow
Drip : a schematic drawing interpreter by Ramsey W. Haddad
Recursive layout generation by Louis M. Monier and Jeremy Dion
Contour : a tile-based gridless router by Jeremy Dion and Louis M. Monier
Case for persistent-connection HTTP