Comments from George Brown:

As for management decisions, the math division under JDW [John D. Williams]

were Rand's "fairhaired" guys. We were already planning on doing the

most advanced computing anywhere, very likely with IBM if they cooperated.

Recall Herman Kahn's shielding calculations, as one example. Game theory

was big, together with linear programming (strongly related). Also recall

that Rand had all the blue-ribbon economists as consultants, and JvN as well.

The 1950 trip to IBM was to push them; we also visited the Moore School and
probably RCA on that same trip, all devoted to finding out what was going
on with high-speed computing. Presumably the decision to build the Johnniac
was because IBM wasn't actively planning to do anything at that time, and
also this might help push them!

The watch incident was much later, I think 1959. Once the decision to build
at Rand was taken, I think I bear at least partial responsibility for
deciding on base-8. I found base-16, which others were planning, to be
ugly. Somehow base-8 looked respectable. I also pushed for the Selectrons
as a way of getting on the air as soon as possible.

The Williams tube memory, which worked OK in a serial machine,

was having all kinds of trouble in the context of a parallel machine.

The fact that I had worked with Rajchman on the Selectron may have
had something to do with the choice, even though RCA was quite reluctant

to do anything with it commercially. BTW, when I was at RCA (1944-6),

Zworykin lent me to Johnny's [John von Neumann's] group that was doing

early planning on the logic of the IAS machine-to-be.

 

The story about core memory efforts at Telemeter Magnetics, using Raymond
Stuart-Williams and Milt Rosenberg (Rajchman's later people), was part of
Ridenour's and my efforts to get into high-speed computing. RCA didn't seem
interested in doing anything with core memory, either!

 

There's an interesting story here about our proposal to build a machine for

the Bureau of Standards:

 

International Telemeter Corporation, a subsidiary of Paramount Pictures
Corp., was formed for the purpose of developing a system of pay-TV, using a
coin box at the set.  Louis N. Ridenour, a famous physicist, left his
position as Dean of the Graduate School at Univ. of Illinois, to take
charge of the pay-TV effort, given Paramount's promise, in return, to allow
him to undertake efforts in high-speed computing equipment.  Ridenour recruited
me from Rand in 1952 to engage in ITC's efforts.  Palm Springs was
to serve as a testbed for the pay-TV effort. In that connection we put an
antenna on a nearby mountainside, with cable installed to bring TV into
town and to distribute signals to a small number of initial subscribers.
This was surely a very early example of cable TV. A successful trial was
made, using a first-run Paramount film transmitted from a studio in Palm
Springs. Paramount apparently had second thoughts, fearing a hostile
reaction from movie theaters, I believe. The pay-TV activity was
terminated!  But that's what I wanted to communicate about the Bureau of
Standards proposal.

 

I'm not quite certain of the dates, but I think we're at 1955, with
Telemeter Magnetics (subsidiary of ITC) busily making core memories for
most, if not all, of the various IAS-type machines in various places. ITC
prepared a proposal to NBS for an innovative computer design, which, as I
recall was massively parallel, with multiple memory units and CPUs.  A
successful negotiation led to a signed contract from NBS sent to ITC. As
one might expect, Paramount's attorneys review the contract and want some
minor nit-pick changes. Now the contract sits on Alan Astin's (NBS
Director) desk, awaiting his signature.

 

Meantime, Dr. Astin comes under attack from a Republican politician named
Weeks, I believe from Newton, Mass. It's not clear to me what Weeks was
after, perhaps to get a buddy appointed to Astin's job?  The attack was
quite mean, in spite of the fact that the Astins were good Republicans, who
rang doorbells to push for Republican candidates (1956 election?). Astin
lets us know that he feels he should not bind his possible successor as
Director, given the fact that he is under fire.  Of course the situation
drags on and on and ultimately the project is abandoned! So much for ITC's
proposal to NBS.

 

ITC made one more serious proposal. It was either to Los Alamos or to
Livermore, I don't now recall. What I do recall is that the laboratory in
question issued a request for proposals, specifying that no chancy
technology should be used, the whole project to be buildable on the basis
of currently-proven techniques. After a suitable period, when they had
received a variety of proposals. they issued, I believe, a new
specification combining all the innovations any proposer had previously
considered, with a request to bid.  ITC prudently refused to bid.

 

George Brown.

 

---

Comments from Mort Bernstein:

 

JOHNNIAC

Johnniac went operational for the first time in the first half of 1953 (no one seems to know the exact date of this event) with 256 40-bit words of RCA Selectron Tube storage, a 40-column numeric printer, a converted IBM Collator for a card reader and a converted IBM Summary Punch. It had
two 19-bit instructions per word with two sets of "transfer" instructions (what are now called jumps or branches), one set to the left half word and one set to the right half word. It had an initial repertoire of 83 instructions (four of which all cleared the accumulator to zero).

 

Later that year, RAND contracted with Telemeter Magnetics for the first commercially built core storage for the Johnniac. The Selectron Tubes were removed in 1954 in anticipation of the installation of the core storage.

 

In March 1955 the machine was back on line with 4096 40-bit words of magnetic core storage. A bit (no pun intended) later that year a 12K drum was installed.

 

In 1956 the analog adder circuitry was replaced with digital transistor logic. Additional transistor circuitry eventually replaced the shift registers and the multiplication and division control logic.

 

In 1957, the 40-column printer was replaced with a 600 line-per-minute

ANelex 120-column (actually, 144-columns of which the JOHNNIAC could only address 120) drum printer with a 56 character repertoire.

 

In 1958 a 30" X 30" flat bed plotter was added.

 

In 1961 a 5-inch scope and the prototype of the RAND digitizing Tablet was added.

 

In 1962 one level indirect addressing was added to the machine using the two heretofore unused bits in the instruction format. Shortly after the machine came back on the air, it was discovered that a number of library programs ran incorrectly because the programmers had used one or both of
the "unused" bits in instruction words as semaphores. A switch was added to the operator's console to disable or enable indirect addressing.

 

That same year, the Multiple Typewriter Communication System (MTCS) consisting of 8 IBM Model B typewriter consoles and drum buffer was added. Additional instructions were added to control the flow of data between the drum buffers and core storage.

 

The Johnniac was decommissioned on February 11, 1966. It had been in service for 13 years and logged over 50,000 operational hours. It was one of the longest lived computers of its era. It spanned the time from the first generation of computers to the advent of the IBM 360.

 

JOHNNIAC Operations as of June 1, 1963

Definitions and Notes

A Accumulator
MQ Multiplier Quotient Register
M Word in Mth address in Internal Storage
A[20-39] Digits in positions 2^-20 through 2^-39 in word in A
c-> Control goes to
& Logical (digit by digit) product intersection

A        copy order (101) directed to the plotter as selected by 100 XXX6 gates only the contents of the specified memory word to the Plotter register with the following meaning:

 

M[0-6] Circle Radius
M[7-18] X Magnitude
M[21-24] Character Selection
M[25] Circle Drawing
M[26] Line Drawing
M[27] Arm Selection
M[28-39] Y Magnitude

Instruction word layout:
M[0-6] Left Operation
M[7-18] Left Address
M[19-20] Left and right address Indirect Address bits. Not used if
Indirect Addressing is turned off via console toggle.
M[21-27] Right Operation
M[28-39] Right Address

 

Op Mnemonic Description
--- -------- -----------
000 NOP Proceed to next instruction
001 TNL If A < 0, c-> left operation in M
002 TPL If A >= 0, c-> left operation in M
003 TFL If overflow, c-> left operation in M
004 LM Clear MQ, M -> MQ
005 TNR If A < 0, c-> right operation in M
006 TPR If A >= 0, c-> right operation in M
007 TFR If overflow, c-> right operation in M

010 TRL c-> left operation in M
011 T1L If T1 on, c-> left operation in M
012 T2L If T2 on, c-> left operation in M
013 T3L If T3 on, c-> left operation in M
014 TRR c-> right operation in M
015 T1R If T1 on, c-> right operation in M
016 T2R If T2 on, c-> right operation in M
017 T3R If T3 on, c-> right operation in M

020 RA Clear A, M -> A
021 RS Clear A, -M -> A
022 RAV Clear A, |M| -> A
023 RSV Clear A, -|M| -> A
024 A M + A -> A
025 S -M + A -> A
026 AV |M| + A -> A
027 SV -|M| + A -> A

030 MR Clear A, M ú MQ rounded -> A
031 MNR Clear A, -M ú MQ rounded -> A
032 M Clear A, M ú MQ -> A and MQ
033 MN Clear A, -M ú MQ -> A and MQ
034 MB M ú MQ + 2^-39 ú [A + «(1[-1] - A[-1])] -> A and MQ
035 MNB -M ú MQ + 2^-39 ú [A + «(1[-1] - A[-1])] -> A and MQ
036 MA M ú MQ + 2^-39 ú A -> A and MQ
037 MNA -M ú MQ + 2^-39 ú A -> A and MQ

040 DS A / M -> MQ, r -> A
041 DNS A / -M -> MQ, r -> A
044 D (A + 2^-39 ú MQ) / M -> MQ, r -> A
045 DN (A + 2^-39 ú MQ) / -M -> MQ, r -> A

050 ST A -> M
051 SOL A[0-6] -> M[0-6]
052 SAL A[7-19] -> M[7-19]
053 SHL A[0-19] -> M[0-19]
054 SAB A[7-19] and A[28-39] -> M[7-19] and M[28-39]
055 SOR A[20-27] -> M[20-27]
056 SAR A[28-29] -> M[28-39]
057 SHR A[20-39] -> M[20-39]

060 STQ Clear A, MQ -> A and M
061 SNQ Clear A, -MQ -> A and M
062 SVQ Clear A, |MQ| -> A and M
063 SNV Clear A, -|MQ| -> A and M
064 AQS MQ + A -> A and M
065 SQS -MQ + A -> A and M
066 AVS |MQ| + A -> A and M
067 SVS -|MQ| + A -> A and M

070 SRC Clear MQ, Shift A right n places, zeros into A[0]
071 CLC Clear MQ, circular shift A and MQ left n places,
couple MQ[0] to A[39] and A[0] to MQ[39]
072 LRC Clear MQ, power shift A and MQ right n places,
couple A[39] to MQ[0]
073 LLC Clear MQ, power shift A and MQ left N places,
couple zeros into MQ[39]; MQ[1] to A[39]
074 SRH Shift A right n places, zeros into A[0]
075 CLH Circular shift A and MQ left n places,
couple MQ[0] to A[39] and A[0] to MQ[39]
076 LRH Power shift A and MQ right n places,
couple A[39] to MQ[1]. A[0] -> MQ[0]
077 LLH Power shift A and MQ left n places,
Couple zeros into MQ[39], MQ[1] to A[39]

100 SEL Select I/O
Address part: XXX0 Primasy Feed Reader
XXX1 Secondary Feed Reader
XXX2 Feed Punch
XXX3 Feed Punch and Echo
XXX4 Select left 80 columns of Printer
XXX5 Select right 80 columns of Printer
XXX6 Select Plotter
101 C Copy; M -> 40 leftmost selected columns
A -> 40 rightmost selected columns
104 DIS Display
105 HUT Hoot
106 EJ Address part: XXX0 Restore one page
XXX1 Advance one print line
XXX2 Advance two print lines
107 Read Clock -> A (Added after June 1, 1963)

110 RD Read Drum words to M and memory addresses following
numerically. Denoting MQ as xxx f1f2f3f4 dpb l1l2l3l4,
the f's determine the first drum address and the l's the
last drum address. d selects the drum, p the position of
the
heads, and b, the bank to read.
111 WD Write M and word in memory numerically following to drum.
The NQ has the same significance as in 110.

120 ZTA Clear A
121 Clear A
122 Clear A
123 Clear A
124 PI M & A -> A
125 NI -M & A -> A
126 PMI |M| & A -> A
127 NMI -|M| & A -> A

130 HTL Halt, c -> left operation in M
131 H1L Halt if H1 on, c -> left operation in M
132 H2L Halt if H2 on, c -> left operation in M
133 H3L Halt if H3 on, c -> left operation in M
134 HTR Halt, c -> right operation in M
135 H1R Halt if H1 on, c -> right operation in M
136 H2R Halt if H2 on, c -> right operation in M
137 H3R Halt if H3 on, c -> right operation in M

140 Write line buffer
141 Read line buffer
142 Write SCR
143 Read SCR
144 Search all SCRs for match
145 Search all SCRs for mismatch
146 Display Graphic I/O
147 Read Graphic I/O Tablet

 

JOHNNIAC Instruction Timing as of 6-6-55

Op Time (micro seconds)
----------------------------------

Fetch 29

000 NOP 30

004 LDQ 36

00X TR(Cond) 31

01X TR(Uncond) 39

02X ADD 80

03X MPY 1400 (max)

04X DIV 1400 (max)

05X STO 35

06X STQ 90

07X Shift 15 + 18n

100 SEL Input device dependent

105 HUT Hoot

11X RD/WD Drum I/O

12X Logical 80

13X Halt

 

 

JOHNNIAC Instruction Timing per Cliff Shaw

Time (micro seconds)
Op Class 3-30-62 4-16-62
-------------------------------------

Fetch 27.9 28.1

00X 35.0 35.0

01X 35.6 35.7

02X 38.0 36.4

03X 388.2-536.0 381.2-474.3

04X 538.0-539.6 471.8-474.0

05X 35.7 35.9

06X 54.7 53.0

07X 19.2 + 8.5n 19.2 + 8.4n

104(Setting 9)14.8 14.6

105 14.2 14.2

12X 38.0 36.4