The Denelcor HEP

NASA Ames Main Auditorium (Building 201),
Moffett Federal Airfield, Mountain View, CA, USA

Reception to follow in
Museum's Visible Storage Exhibit Area (Building 126)

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ABSTRACT OF TALK

The Denelcor HEP was a uniform shared memory multiprocessor that used fine-grain multithreading to tolerate memory latency, synchronization latency, and even functional unit latency. Six systems were delivered to customers during the years 1981-1985.

This talk will describe the evolution, innovations, and disasters that accompanied the development of hardware and software for the HEP.

BACKGROUND OF SPEAKER

Throughout his long and distinguished career, Burton J. Smith has made major contributions to the field of parallel computation, primarily in the area of high-speed, general purpose computer architecture. "The most credible solution to the dilemma facing the supercomputing industry is to narrow the gap between supercomputers and general purpose systems," he says. "As designers of general-purpose systems increasingly turn from uniprocessors to small-scale multiprocessors in order to provide higher performance, a reunification between general-purpose computing and supercomputing may even become possible."

A renowned supercomputer architect, Smith believes that the best architectural course toward such a reunification is one that uses multithreaded processors to build scalar supercomputers with true shared memory. "Multithreaded supercomputer systems can be built that provide exceptional scalar performance, true shared memory, and scalability to many processors," Smith says. "Systems with these characteristics can enlarge the supercomputer market by supporting a broader spectrum of scientific computing. Such systems can also provide a platform for commercial applications such as computer-aided design and large data bases."

Smith is the primary architect of Tera Computer Company's MTA system, a high-performance, multithreaded, multiprocessor system intended for general-purpose applications. According to Smith, Chairman and Chief Scientist of the Seattle-based company since 1988, and now of Cray Inc., the MTA represents a significant breakthrough in high-performance computing and offers improvements over conventional vector multiprocessors and massively parallel systems. "The architecture is scalable and general purpose, meaning that users can easily add processing power without reprogramming," Smith explains. "The processing speeds are available to a wide variety of computational problems, including scientific and engineering computations, data base applications, and image rendering."

Smith was also the primary architect for what was another ground- breaking system in the early 1980s, the Denelcor HEP. The HEP was the first commercial system designed to apply multiple processors to a single computation, and the first to have multithreaded CPUs. Smith, Denelcor's Vice President of Research and Development from 1981 to 1985, also designed part of the HEP's hardware, including the interconnection network, and funded the development of automatic parallelizing compilers for the system.

Smith has not only made important contributions to the high-performance computing industry, but has also taught and conducted research in academia during his career. After receiving his BSEE from the University of New Mexico in 1967 and his ScD from the Massachusetts Institute of Technology (MIT) in 1972, he was an assistant professor of electrical engineering at the University of Colorado. In 1978 he became an associate professor, then left the university in 1979 to join Denelcor in Colorado.

As a graduate student, Smith was an electrical engineering instructor at MIT and a consultant to the New Hampshire-based Hendrix Electronics Corporation. In addition, Smith founded and directed the Scientific Electronics Corporation in Massachusetts from 1969 to 1970, and was Institute for Defense Analyses (IDA) Supercomputing Research Center Fellow from 1985 to 1988.

Smith has been involved in many professional and advisory activities, including the NSF Panel on Large-Scale Computing in Science and Engineering (1982), NSF Division of Computer Research Advisory Committee (1984 to 1987), Organizing Committee for the SIAM Conference on Parallel Processing for Scientific Computing (1987), Editorial Board of the International Journal of Supercomputing Applications (1987 to 1989), the Presidential Faculty Fellows Final Selection Panel (1992 and 1993), and the NSF Blue Ribbon Panel on High Performance Computing (1993). His honors include Eta Kappa Nu, Sigma Xi, NSF Graduate Fellow (1968 to 1969), IEEE-ACM Eckert-Mauchly Award (1991), IEEE Fellow (1994), and ACM Fellow (1994). He is the author or co-author of more than 50 papers.