IBM 1620 Project Journal
PE Principles of Operation
David Wise
26-Mar-1999
Changes since 3-Mar:
1. More timing discussion. The addition of individual algorithms
made the "Simplified Main Loop" outdated and redundant.
The main loop just watches for status bits that mean we need
to run one of the algorithms.
2. RcvD and RcvF are renamed P2 and P4, and PFeed and PNoFeed trade
places. This does not change the board layout, it just renames
existing nets. This makes the punch emulation look exactly like
a real punch.
3. Punch data connections renamed so bits go 1 2 4 8 C O X
to match reader format. This was only a net-rename, and does
not affect the board layout. Because I renamed the same lines
in the Paper Tape emulation and Monitor sections, we can still
wire the two cables the same.
4. Card P1D mux handled by 74LS245 instead of passive diode switch.
This increases speed while reducing package count. I wish I
could cut the Paper Tape board package count (speed is not an
issue) but the layout is too far along.
5. Don't have to treat SIE button as SPDT.
6. Shifted typewriter "2" is paired with unshifted "I" not "L".
7. MAR DISPLAY SELECTORs are S-level not T-level on F-suffix machine.
8. SAVE and DISPLAY MAR buttons are S-level not T-level on
F-suffix machine. I moved them from CBR to CMR.
9. Added Paper tape and Card board presence detection algorithms.
10.Released all but one page of card schematics.
INTRODUCTION
This PC software and hardware emulates the 1620 console typewriter,
the 1621 paper tape reader and 1624 paper tape punch ("1621" for
short), and the 1622 card reader/punch. In addition, it provides
remote control of the 1620 front panel switches and buttons,
and can drive a real 1621/1624 for archiving.
The PC connects to a 6U VME card cage via two LPT cables. The cage
in turn connects to Shoe Connector A (the 1620's paper tape signal
connector), CXA/CXB (the typewriter connectors), a sheaf
of wires attached to the console switches, the 1621's
Shoe Connector, and SCB/SCC, the 1620's card signal
connectors. The cage contains its own +5/+12/-12V supply,
but gets +48V from the 1620's console switch wiring, from CXB, and
from SCA.
Ground is established through the Console cable, the Paper Tape cable,
and the Card cables. (CXA contains a ground but it is unsatisfactory.)
The console and Shoe Connector A sport no grounds; the ground wires in
those cables split off from the rest of the cable and tie to
the 1620 DC Ground bus.
HARDWARE DESIGN
The 1620 peripheral emulator connects to a PC via two LPT ports, which
I refer to as LPT0 and LPT1. Each board plugs into the VME
backplane via two Euro96/DIN plugs called P1 and P2.
Each P2 jack goes through the backplane alone and comes out on a plug
in back. We bus P2 ourselves, via a ribbon cable which plugs into all
the P2s at one end, and splits and goes to two bulkhead LPT jacks
at the other. We use P2 rather than the already-bussed P1, because P1
has termination resistors which would have to be unsoldered. We use
P1 only for power and ground.
At the PC, each LPT port has 8 data bits (D[0:7]), 4 control outputs
(C[0:3]), and 5 status inputs (S[3:7]). LPT1 must support Bidirectional
operation. If both ports are bidirectional, the software can determine
which port is which and automatically adapt.
Sim21 on-board components are 74LS273 octal flip-flops, 74LS138
3-to-8 decoders, 74154 4-to-16 decoders, 1488/1489 RS232
drivers/receivers, UDN2983, ULN2023, and UDN2588 power drivers,
8-bit resistor packs, hundreds of diodes (I couldn't get a
supplier for diode packs) and a few other discretes. The UDN2983
drives grounded (or negative-based) loads to a positive voltage,
+12V or +48V in sim21. It's used mostly to drive the console buttons
and the typewriter relays. The UDN2588 drives negative-based loads to
ground. We use it to drive the console switches. The ULN2023 drives
positive-based loads to ground. We use it to run the 1621 punch magnets
and other sink applications.
The design is modular and consists of:
1. Typewriter board
(Champ50 cable to CXA, DB15 cable to CXB, DB25 and DB15 cables to
the front panel)
2. Paper tape board (Champ36 cables to SCA and 1621)
3. Card board (Champ36 cables to SCB and SCC). If we can get
block connectors but not Shoe connectors, we can bypass them
and go directly to the D Gate block connectors.
The typewriter board can operate alone. If other boards
are present, the typewriter board must be present too.
ASSUMPTIONS
1. One of the LPT ports is capable of Bidirectional operation.
2. In Input mode, the LPT data lines are high-Z.
3. LPT data outputs can drive 10 LSTTL loads.
4. LPT status inputs need external pullups.
5. SCR V(On) <= 2V.
6. SCR I(Hold) <= 10mA.
SCHEMATICS (Sheets are numbered in filename alphabetical order)
A. CARD BOARD
A.1 c_con. J1 (Champ36 to Shoe Connector B) and
J2 (Champ36 to Shoe Connector C).
A.2 c_ctrl. Status drivers to the 1620.
U2 (74LS273) is the Card Control Register (CCR).
It is clocked with P0D by the P1C2 falling edge and
cleared by RST from the Console board.
The CCR drives (via U4 and U5, 1488 RS232 line drivers)
8 status lines to the 1620, plus status and data mux
control lines (see c_stat). This is more than 8 bits.
I found a set of lines that were mutually exclusive
(C_RSync, C_PSync, C_PDscn, C_Last, and C_Load),
and decoded them via U3, a 74LS138 3-to-8 decoder.
This takes care of 5 lines. The other 5 operate together or
in conjunction with zero or more decoded lines.
Since C_RSync is gated against C_RRdy, software can
clear the C_RSam flip-flop (see c_stat) without
disturbing the 1620. This makes Card board presence
detection easy. If the board is absent, P0S4 will
float TRUE. If the board is present and the flip-flip
is clear, P0S4 will read FALSE.
We need special timing for Read Disconnect. It must
occur right on the MDR SAM I/O leading edge.
We do this with U7. If CCR[5] is true at MDR SAM I/O
(driven by c_stat as P1S4), U7 drives
-C CARD RD DISCONNECT until we clear CCR[5].
Since 1488s invert and all the lines to the 1620 are
low-true, the '138 outputs need inversion (U6) so a
clear CCR transmits an idle/not ready state to the 1620.
C_RSync and C_PSync go through U1, a 74LS123 dual one-shot,
on their way to the 1620, because software can't
generate the 8uS pulses needed. Their outputs are gated
against C_RRdy and C_PRdy, respectively, to guarantee
that the 1620 does not receive spurious sync pulses
during emulator power-on and Card board presence detection.
U4 and U5 have a 10mA output current limit. The 1620
has an asymmetrical termination (120 ohms to ground plus
1.5K to +12V) which must be compensated so our symmetrical
drive can achieve the best noise margin. RP1 (1.5K to -12V)
does this. With this termination, the 1488s will drive
+1V/-1V, the levels reached by the 1620's DED and DEE cards.
The IBM documentation claims that the negative level is
-2V, but that is wrong.
U4 and U5 dissipate too much power if they
drive all outputs to current limit. By adding
470 ohm series resistors (RP2) we move about
half of that heat out of the ICs.
A.3 c_drv. Data drivers to the 1620.
U8 (74LS273) is the Card Data Register (CDR).
It is clocked with P0D on the P1C2 rising edge and
cleared by RST. It drives 7 data lines (1248CAB)
to the 1620 via two more 1488s, U9 and U10, with
series resistor RP4 and shunt resistor RP3 a la c_ctrl.
A.4 c_p2. VMEBus P2 connector and LPT status line pullups.
P2 is a 96-pin Euro/DIN plug.
The outer two rows are cabled to the PC LPT ports.
Three LPT lines in each cable are ground.
The center row has Vcc and ground from the card cage.
The LPT port status lines (P0S and P1S) have weak (2.2M)
pullups. We reinforce the P1S pullups with RP5.
We don't use P0S.
A.5 c_rcv. Data receivers from the 1620.
U11 and U12 (1489) translate the 1620 +C/-C data signals to
TTL and put them on P1D via U13 (74LS245*).
If we terminate the 1620's DED cards with 150 ohms to
ground (RP6), they will drive 0V/-2V, so we set the 1489
threshold to -1V with RP7.
* The 74LS245 is a bidirectional tri-state driver, but
we only use one direction. We use the '245 instead of
the unidirectional '244 only because it is available
at Wacky Willy Surplus.
Since U13's enable is low-active, we invert it via U6
so a clear MCR tri-states the driver. You MUST disable
U13 when any other P1D source is enabled.
A.6 c_stat. Control line receivers from the 1620.
U? and U? (1489) translate 1620 +C/-C control signals to
TTL and put them on P1D via U?. When we don't want this
data, we disable U? via U6.
Because of their short pulse width and critical timing,
C_RSam and C_PSam set flip-flops (U?, 74LS74) which go
to LPT status lines. C_PSync clears the C_PSam flip-flop,
and C_RSync clears the C_RSam flip-flop.
A.7 card. VMEBus P1 connector. This is the WinDraft "master"
sheet for the card board.
B. PAPER TAPE BOARD
B.1 p_con. J1 (Champ36 to 1621) and
J2 (Champ36 to Shoe Connector A).
We can't cut the heads off standard LPT cables, because
we use more than the standard number of conductors.
LPT "extension" cables might work, have to ohm one out.
B.2 p_mdrv. Reader and punch drivers to the 1621.
U1 and U2 (74LS273) are the Monitor Data Register (MDR) and
Monitor Control Register (MCR). They are clocked with P0D
on the P0C2 L-H and H-L transitions and cleared by RST.
They control two ULN2023 sink drivers (U4 and U5)
and a 1488 (U6). MDR runs the punch data solenoids,
MCR the punch Feed/NoFeed solenoids, the reader clutch,
and P1D mux select.
The punch contains solenoids hanging from +48V. U4 and U5
ground the other end. The punch lines are split between
U4 and U5 to equalize power dissipation. In addition to the
Feed and NoFeed punch lines, U5 controls SMux and DMux,
which when sinked, ground out the Status and Data
multiplexer, respectively. Since ULN2023s invert, we
invert the SMux and DMux lines with part of U3 (74LS04), so
a clear MCR will ground both data sources. Finally, U5
controls the reader clutch via part of U3 and U6. The extra
inversion through U3 ensures that a clear MCR leaves the
reader idle.
B.3 p_mrcv. Reader data receivers from the 1621.
U7 and U8 (1489), their 1/0 thresholds shifted to about -5V
by RP1, listen to the reader data outputs, which are PNP
collectors with resistive pulldown to -12V. 1489 input
impedance is around 4K, which with the 1621's 1.6K output
yields about -9V. 1489 outputs are NPN collectors with
2K resistive pullup to Vcc. This pullup, plus DP1's diode
drop, plus the 10K termination pulldown, yields 3.6V which
meets the TTL Voh spec at P1D. When we don't want this
data source, we ground it via DMUX and DP2, and DP1 isolates.
B.4 p_mstat. Reader and punch status receivers from 1621.
This is identical to p_mrcv except the inputs are
Non-Process Runout from the reader, and Tension,
Clock (P3 and PCB1), Error, and Manual Feed from the punch.
All these signals have the same characteristics as the data
signals so they are received and muxed (by SMUX) the same way.
Reader clock and reader ready go directly to LPT status
lines, the former because its timing is critical, the
latter due to my error. I won't annoy my board layout
volunteer by changing it back.
B.5 p_p2. VMEBus P2 connector and LPT status line pullups.
P2 is a 96-pin Euro/DIN plug.
The outer two rows are cabled to the PC LPT ports.
Three LPT lines in each cable are ground.
The center row has Vcc and ground from the card cage.
The LPT ports have very weak (2.2M) status pullups which are
reinforced here. We only pull up P0S because we don't
use P1S.
B.6 p_pctrl. Status line drivers to 1620.
U11 is the Paper Tape Control Register (PCR). It's clocked
with P0D on the P0C1 L-H transition and cleared by RST.
It sends reader and punch status to the 1620 via U13 and U14,
a pair of 1488s with their 10mA current-limited outputs
clamped to ground by DP5. 10mA is plenty to drive the 1620's
5.6K input impedance to "-S". The clamp keeps it from going
above +S. Inverters make a clear PCR drive all signals to
inoccuous states: we claim the reader is not ready and the punch
made an error, has a broken tape, and is mechanically idle.
The PCR also drives two signals that do not go to the 1620,
P4 and P2. These drive (via U18 on p_pstat) two
SCR pullups described on pages p_prcv and p_pstat.
For timing reasons we control RSync directly from P0C0.
The 1620 clocks data on the P0C0 L-H transition.
I ran out of PCR bits, so we don't emulate Non-Process Runout.
It's also pretty meaningless to emulate it.
B.7 p_pdrv. Reader data line drivers to 1620.
U12 is the Paper Tape Data Register (PDR). It is clocked
with P0D on the P0C1 H-L transition and cleared by RST.
It drives a pair of clamped 1488s. These eight lines
are the eight tape channels, 1 2 4 8 C O X EL.
B.8 p_prcv. Punch data receivers from 1620.
This P1D source, controlled by +12_P2 (P2 from p_pctrl
run through U18, a +12V source driver on p_pstat), is the
1620's punch data outputs. The 1620 contains SCRs meant
to sink-drive solenoids hanging from +48V, but +12V will do
because RP4 sources enough current to keep the SCRs latched.
SCRs have a much higher Von than transistors, as much as 2V.
RP3 and RP5 level-shift this down to 1V, and the drop through
isolating diode DP7 gets us to TTL Vol. If the SCR is off,
the network output is clamped to +5V by the termination
network on t_p2. If +12_P2 is not driven, the
network back-biases DP7 to not interfere with other data
sources, and negative leakage through RP5 is routed away
from the SCRs by a catch diode in U18.
B.9 p_pstat. Control line receivers from 1620.
This page contains a 1489 (U17) which translates the reader
and punch clutch lines and the punch no-feed line (used by
the 1620 to prevent tape advance past an erroneous punch)
into LPT status signals.
R1 shifts U17's reader clutch receive threshold to -5V.
R4 and R5 shift the punch receive thresholds to around +6V.
When an SCR is on, its output is +2V or less.
When off, it rises to around 10V (not 12V; the 1489 loads it).
U17 drives P0S7 low (i.e. 1 in the LPT status register)
when the 1620 wants reader data, P0S5 and P0S6 high
(i.e. 1) when the 1620 wants the punch
to run and no-feed, respectively.
U18 (UDN2983) translates the PCR's P4 and P2 signals to
+12V source drive. If all SCRs are on, the load is 90mA.
+12_P2 drives the Data pullups (on p_prcv) and the Feed pullup.
The 1624 drives these together from its P2 cam.
NoFeed is pulled up by +12_P4, which duplicates the 1624's P4 cam.
B.10 paper. VMEBus P1 connector. This is the WinDraft "master"
sheet for the paper tape board.
C. TYPEWRITER BOARD
C.1 t_ccon. J2 (Console) connector.
J2 is a DB25F connector which carries +48V, ground,
and 16 lines to drive console switches and buttons.
+48V is obtained from the console button common terminal.
Ground is obtained from the 1620 DC ground bus.
C.2 t_cdrv. Console drivers.
U3 and U12 are the Console Switch Register (CSR) and
the Console Button Register (CBR). They are clocked
with P0D on the P1C0 falling and rising edges and
reset by RST.
Con0-7 are the console switches. In the 1620 they have
an 820-ohm pulldown to -12V. A closed switch grounds.
We do that with U1, a UDN2588 source driver with its
output Vcc tied to ground. Its Vs line is set at
+3.6V so TTL Voh is interpreted as 1.
Because U1 inverts, we must invert its inputs
(with U4 and part of U5) so a clear CSR = all switches off.
The driver outputs are in parallel with the physical
switches, which must be turned off to use the emulator.
The UDN2588's internal structure makes backdrive
up to and including its Vcc harmless.
Con8-15 are most of the console buttons (see t_cmar).
In the 1620 they are pulled to -12V by 3.3K RC integrators.
A closed button drives +48V. We do that with U2, a UDN2983
source driver.
The button drivers are in parallel with the existing
buttons, via DP1 to prevent damage from backdrive.
The SIE and SCE buttons are SPDT, but the NC contacts
are used only for debouncing (when open they prevent the
Start Ctrl trigger from clearing). In the absence of bounce,
closing the NO and NC contacts simultaneously is equivalent
to closing just the NO contacts. This means we don't need
to disconnect any switch wires.
C.3 t_cmar. MAR Display Selector drivers (and SAVE/DISPLAY MAR).
CMR (U16, 74LS273) is clocked with P0D on the P0C3 falling
edge and cleared by RST.
Unlike the other buttons, which are driven at +48V,
SAVE and DISPLAY MAR are ground-based. Since the
MAR DISPLAY SELECTOR switch uses a theoretical maximum
of 13 lines, and we have 16, we use the extras to
drive SAVE and DISPLAY MAR.
J1 carries 16 lines to the MAR Display Selector switch
and the SAVE and DISPLAY MAR buttons. I ran out of
connector space on the board edge, so it is a 16-pin
dual-row header located inland. It goes via ribbon cable to
an IDC DB15F on the typewriter board's double-wide front panel.
U16's four low-order bits are decoded into 16 lines by
U17, a 74154. Lines 0 through 12 (and line 15) go to the
1620 via U14 and U15, a pair of UDN2588 negative load
source drivers. Lines 1 through 11 go to the MAR DISPLAY
SELECTOR switch, which is ground-based with 820 ohm
pulldowns to -12V. Lines 0 and 12 are spares.
U17 line 15 drives the SAVE button. All other buttons are
controlled by independent register bits, but register
bits must be inverted before going to a UDN2588 and I
used the last inverter for the DISPLAY MAR button, so
rather than adding another 74LS04 I departed from convention
and put the SAVE button on U17, which has low-active outputs.
The 12-position MAR DISPLAY SELECTOR switch has one unused
position, to which we set it when using the emulator.
On a 1620 using all 12 positions, we would break the
switch common and reroute it to line 0, and apply a
shorting plug when not using the emulator.
When 1, U16 bit 4 disables U17, setting all its outputs high.
This is not used for anything, but it eases board layout.
U16 bit 5 is unused. U16 bit 6 drives a spare output which
is the wrong polarity (low-active) and does not come out on
the emulator front panel DB15 connector.
U16 bit 7 drives (through inverter U5D) the DISPLAY MAR
button.
On D. Wise's B-suffix machine, all switches and buttons are +T.
The UDN2588 drivers can still be used, as long as they are
connected to the RC integrator outputs instead of the inputs.
The only issue is ground bounce from driving the integrator's
4.7uF capacitive loads.
C.4 t_p2. VMEBus P2 connector, LPT P1 Data signal termination,
and Power-On Reset.
P2 is a 96-pin Euro/DIN plug.
The outer two rows are cabled to the PC LPT ports.
Six LPT lines are ground. The center row has Vcc and
ground from the card cage.
The P1D lines have 10K pulldowns to ground and diode clamps
to Vcc to terminate the passive diode multiplexer through
which we receive most 1620 signals. Since most of the
multiplexed signals are high-voltage positive, we
protect the PC from voltages over 5V with diode clamp DP2.
The 10K value of RP3 is a compromise between signal fall time
on the LPT cable and output voltage from those data sources
being pulled up only to +5V. The fastest device we must
keep up with, the 1621 reader, is only 150Hz so P1D fall
time is not critical. If you want to speed it up for
other transfers, before each read briefly configure P1D
to output mode and drive 0s to discharge the line
capacitance. You will of course have to wait for a "1"
to charge it back up, but this happens through a much
smaller impedance. I figure on a 5x speedup.
Register reset is accomplished at power on by U7, a
Dallas Semiconductor DS1233 "Econo-reset" chip. It
furnishes a 300mS low pulse with a resistively pulled-up
open-collector output. This output clears all registers
on all boards. The RST line goes to the other boards via
P2 on a line unused by the LPT ports.
C.5 t_tcon. J1 (CXB) and J3 (CXA) connectors.
DB15F and Champ50F, respectively. CXB is +48V-based
typewriter contacts talking to the 1620, CXA is the 1620
driving ground-based 48V solenoids in the typewriter.
The typewriter has a contact for every typebar, but the
1620 encodes them down to XO8421, and for each of those
7 bits there is a contact that lights exactly one of them,
which allows us to drive those 7 lines instead of all 43.
C.6 t_tctrl. Typewriter control.
U8 (74LS273) is the Typewriter Control Register (TCR).
It is clocked with P0D on the P1C1 rising edge and cleared
by RST. It emulates (via U6, a UDN2983 +48V source driver)
the typewriter's Shift, Tab, Last Column, and Selector
Common 1 and 2 contacts.
On the real typewriter, SC1 is powered by a contact on
the STORE relay, which is only on during input.
The emulated SC1 is always powered. Software must never
set TSC1 except during STORE.
We do not emulate the typewriter Release/Start key
because (a) I ran out of wires and (b) our control
of the front panel Release and Start buttons makes it
redundant. If you made up an adaptor plug for the
Museum's cable, you could reuse the t_tdrv Backspace
output as R/S.
U8 also controls U10 (a 74LS138 3-to-8 decoder) and U11
(ULN2003 or ULN2023 sink drivers). Depending on TCR[0:2],
one (or possibly none) of the typewriter data sources are
enabled.
C.7 t_tdrv. Typewriter data.
U13 (74LS273) is the Typewriter Data Register (TDR).
It is clocked with P0D on the P1C1 falling edge and
cleared by RST. It emulates (via U9) the typewriter's
Flag, X, O, 8, 4, 2, and 1 contacts.
As a special feature for David Wise's 1620
(which supports backspacing over incorrect typewriter
input), U9 also emulates a Backspace contact on CXB38.
Since on standard typewriters CXB38 is Space Interlock 2
(which in late 1620s is tied to Selector Common 2),
a diode protects U9 from backdrive.
The real typewriter contacts are powered by SC1. Emulation
software must not drive them unless TSC1 is true.
When we stop driving +48V to a ground-based relay, it will
produce a negative inductive kick. The UDN2983 has catch
diodes to clamp this to ground, but they go to logic
ground -- the last place we want bouncing around. To stop
the kick before it reaches ground, we actively clamp the
lines to 0.7V with Q4, DP3, and related circuitry. Q4's
collector is on +48V, the one supply whose noise level is
unimportant. Any time a relay kicks, the spike travels back
to the 1620 on +48. Each relay coil is 700 ohms.
Because Q4 dissipates around 1/2W when
idle (48*(0.7/(700/8))), it is on a heat sink.
C.8 t_trcv1. Typewriter receivers.
The typewriter has a solenoid under each key and
for space, shift, tab, CR, and KB unlock (a.k.a. Store).
The 1620 drives them with +48V through relay contacts.
Each byte of solenoid bits goes through a 10K dropping
resistor and a series diode. If the line is high
(i.e., +48V), about 4mA goes through the series resistor
and diode, driving P1D against the diode clamps on t_p2.
If the line is undriven, the P1D bit is pulled low by its
10K termination resistor (also on page t_p2). A high input
can be overridden by pulling the cathode of the associated
shunt diode array low, which is done by the TCR, U10, and
U11 on t_tctrl.
To look at a specific byte, set TCR[0:2] to 1 through 6 to
get mux banks 1 through 6. You must set TCR[0:2] to 0
after browsing the typewriter data so as not to interfere
with other data and status reads.
C.9 t_trcv2. More Typewriter receivers, same as t_trcv1.
C.10 type. VMEBus P1 connector, supplying power and ground.
This is the WinDraft "master" sheet for the typewriter board.
PROGRAMMING
LPT PORTS
Base can be 378, 3BC, 278, 2BC. Some PhoenixBIOSes allow 228.
Data = Base + 0 Becomes high-impedance in input mode.
Status = Base + 1
Command = Base + 2 Bit4 = IRQE, Bit5=Direction (1=Input)
ECR = Base + 402 (Only when BIOS configs SIO LPT as ECP)
Set ECR[7:5] to 001b to set Bidirectional Mode.
25 36 Bit Inverted Name
1 1 C[0] X H Strobe
2:9 2:9 D[0:7]
10 10 S[6] Ack
11 11 S[7] X Busy
12 12 S[5] PE
13 13 S[4] Selected
14 14 C[1] X H AutoFeed
15 32 S[3] Error
16 31 C[2] H Init
17 36 C[3] X L Select
18:25 17, 19, 26 Ground
NOTE: "L" and "H" refer to the just-booted state of the command signal.
Signals marked X are inverted with respect to the bits in the register.
The values shown correspond to a command register value of 0xC.
REGISTERS
P0D drives the PCR, PDR, TCR, TDR, CSR, CBR, MDR, MCR, CCR, and CDR.
P1D is configured to Input mode and receives multiplexed data
from the 1620 and 1621.
Assert by writing ------v-----------------------v
C[0] RSync 1 ConEn 1
C[1] PEn 1 TEn 1
C[2] MonEn 1 CardEn 1
C[3] MarEn 1 Reserved
TRUE when you read -----v-----------------------v
S[3] M_RSync 0 C_PSam 1
S[4] M_RRdy 1 C_RSam 1
S[5] PFeed 1 Reserved
S[6] PNoFeed 1 Reserved
S[7] RClutch 1 Reserved
CARD
LPT CONTROL LINES
CardEn(P1C3) Clocks P0D into CDR on its 0-1 transition,
and into CCR on its 1-0 transition.
CARD DATA REGISTER (CDR)
CDR[0123456] Drives -C [1248CAB] BIT 01.81.15.[123] to the 1620.
Set this at least 14uS before setting C_RSync.
CARD CONTROL REGISTER (CCR)
Bit What
0-2 C_Out[0:2] Decodes to one of five possible outputs
3 C_RRdy -C CD RD BUFF READY 01.80.30.1
4 C_PRdy -C CD PUNCH BUFF READY 01.80.20.1
5 C_RDscn -C CD RD DISCONNECT 01.80.20.1
6 C_SMux C_S[0:5] -> P1D
7 C_DMux C_D[0:6] -> P1D
C_Out What
0 No output
1 C_PSync -C CD PUNCH SYNC 01.80.20.1
2 C_RSync -C CD RD SYNC 01.80.30.1
3 C_PDscn -C CD PUNCH DISCONNECT 01.80.20.1
4 C_Last -C LAST 1622 CARD 01.80.05.1
5 C_Load -C CD RD LOAD 01.80.10.1
6 Reserved
7 Reserved
CCR OUTPUTS
C_DMux Gates data onto P1D.
C_Last Sets the 1620 Last Card indicator. Assert after
C_Exit for 15uS if there's no more reader data.
C_Load Causes the 1620 to read one card and execute it. Assert
for 15uS, only if C_Manual is true and C_RCheck
and C_Reset are false. The signal is blocked if
C_RRdy is false.
C_PDscn Causes the 1620 to Disconnect from a write or dump.
After reading the final data byte, assert C_PDscn for 15uS.
C_PRdy Tells the 1620 you can accept punch data.
At the 1620 it gates CD PUNCH DATA GATE and the
Punch No Feed lamp.
The 1622 removes CD PUNCH BUFF READY simultaneously
with asserting Disconnect and keeps it off until it has
punched the card and brought a fresh one into place.
C_PSync Triggers a one-shot which pulses CD PUNCH SYNC, which
tells the 1620 that we want to receive a byte of data.
The pulse is not transmitted to the 1620 if C_PRdy is false.
C_PSync also clears C_PSam.
C_RDscn Causes the 1620 to Disconnect from a read.
When you set this bit, the next SET MDR SAM I/O will set
a flip-flop which drives CD RD DISCONNECT. The flip-flop
is cleared when you clear C_RDscn.
If you set this bit from the 80th C_RSync until C_Exit,
you will duplicate the 1622's behavior.
C_RRdy Tells the 1620 you have read data buffered and
ready for transfer. At the 1620, this line gates
CD RD DATA GATE and the Reader No Feed lamp.
C_RSync Triggers a one-shot which pulses CD RD SYNC, which
tells the 1620 that a byte of data is available.
The pulse is not transmitted to the 1620 if C_RRdy is false.
C_RSync also clears C_RSam.
C_SMux Gates status onto P1D.
P1D INPUTS
C_D[0:6] Receives -C 1620 [1248CAB] BIT from the 1620. The
data is gated onto P1D by C_DMux. TRUE when you read 1.
C_S[0:6] Receives control signals from the 1620. The data is
gated onto P1D by C_SMux.
Bit TRUE= Receives IBM Name
0 1 C_RGate -C CD RD DATA GATE 01.80.30.1
1 0 C_RCheck -C RD CHECK TGR OFF 01.81.45.1
2 1 C_PGate -C CD PUNCH DATA GATE 01.80.20.1
3 0 C_PCheck -C WR CHECK TGR OFF 01.81.45.1
4 1 C_Exit -C I/O EXIT TGR 01.81.15.1
5 1 C_Reset -C MANUAL RESET 01.80.05.1
6 1 C_Manual -C RUN TGR OFF MANUAL STATUS 01.80.10.1
C_RGate Tells us the 1620 wants to read a card.
It holds it TRUE until Disconnect. When the 1622 sees
CD RD DATA GATE, it sets up the first data byte and pulses
CD RD SYNC.
Negating C_RRdy blocks this signal.
C_RCheck Tells us the 1620 got a parity error. It blocks the
1622 reader from buffering the next card. The signal
comes at the same time as the offended C_RSam and stays
on until reset in the 1620. We sample it just after
C_Exit.
C_PGate Tells us the 1620 wants to punch a card. The 1620
holds it TRUE until Disconnect.
Negating C_PRdy blocks this signal.
C_PCheck Tells us the 1620 got a parity error. At Disconnect,
it makes the 1622 reject the current punch buffer contents.
Once on, it stays on until reset in the 1620. We sample it
after Disconnect.
C_Exit Tells us the 1620 is done with the I/O instruction.
It causes the 1622 to clear CD RD DISCONNECT,
and if CD RD CHECK TGR OFF, read the next card.
When punching, the 1622 reacts to Disconnect rather than
Exit, because one instruction (DNCD) may punch multiple cards.
C_Reset Somebody's pressing the 1620's RESET button. Clear
everything if true.
C_Manual Tells us the 1620 is idle. Do not assert C_Load unless
this bit is true.
LPT STATUS LINES
C_RSam The 1620 asserts MDR SAM I/O to clock a byte of card reader
data into memory. The pulse is too short to reliably capture
in software, so hardware sets a flip-flop whose output is C_RSam.
The flip-flop is cleared by C_RSync.
Since we do not set C_RSync after the final C_RSam, C_RSam will
remain TRUE until the first C_RSync of the next card read.
C_RSam is TRUE when you read 1.
C_PSam The 1620 asserts I/O SAM MDR to clock data into the 1622.
Like C_RSam, the pulse is too short to capture,
so it sets a flip-flop whose output is C_PSam.
The flip-flop is cleared by C_PSync.
Since we do not set C_PSync after the final C_PSam, C_PSam will
remain TRUE until the first C_PSync of the next card write.
C_PSam is TRUE when you read 1.
ALGORITHM (Card board presence detect)
Clear C_RRdy ; Prevent C_RSync from reaching 1620
Set C_RSync ; Clear C_RSam
Clear C_RSync
If C_RSam == TRUE ; LPT status line floating high
Board is absent
Else
Board is present
ALGORITHM (Card read)
(If unable to read from card source file, clear C_RRdy)
(This routine is entered when C_RGate goes true)
(Abort out on C_Reset or !C_RGate)
80 times
{
Store byte in CDR ; Present data to 1620
Wait 15-30uS ; To meet 1620 data setup time
Select C_RSync ; Trigger one-shot, clear C_RSam
Select None ; Remove trigger
If last char, set C_RDscn ; Arm Dscn FF
Wait for C_RSam
}
Wait for C_Exit ; Disconnect causes Exit
Clear C_RDscn
If not C_RCheck
{
Clear C_RRdy ; While we get next card
If not EOF
{
Buffer next card
Set C_RRdy ; Next card is on-line
}
else
Select C_Last ; Set LAST CARD Indicator
Wait 15-30uS
Select None
}
ALGORITHM (Card punch)
(If unable to write to card sink file, clear C_PRdy)
(This routine is entered when C_PGate goes true)
(Abort out on C_Reset or !C_PGate)
80 times
{
Select C_PSync ; Trigger one-shot, clear C_PSam
Select None ; Remove trigger
Wait for C_PSam
Clear C_Status
Set C_Data ; Prepare to read data
wait 15-30uS ; Wait for mux
Read char from P1D
Clear C_Data
Set C_Status ; Prepare to read status
Wait 15-30uS ; Wait for mux
}
Clear C_PRdy ; Off-line while we punch
Select C_PDscn ; Signal last byte xferred
wait 15uS
Select None
If not C_PCheck
Store card
Set C_PRdy ; Ready to receive next 80
CONSOLE
LPT CONTROL LINES
ConEn(P1C0) Clocks P0D into the CSR on its 0-1 transition,
and into the CBR on its 1-0 transition.
MarEn(P0C3) Clocks P0D into the CMR on its 0-1 transition.
CONSOLE SWITCH REGISTER (CSR)
Bit What
0 Reserved
1 +S DATA CHECK SW AUTO 01.05.02.1
2 +S I/O CHECK AUTO 01.05.02.1
3 +S OVERFLOW CK AUTO 01.05.02.1
4 +S SENSE SW 1 01.05.02.1
5 +S SENSE SW 2 01.05.02.1
6 +S SENSE SW 3 01.05.02.1
7 +S SENSE SW 4 01.05.02.1
CONSOLE BUTTON REGISTER (CBR)
Bit What
0 CONSOLE RESET 01.05.03.1
1 INSERT 01.05.01.1
2 RELEASE 01.05.01.1
3 Reserved
4 START 01.05.01.1
5 INSTANT STOP/SCE 01.05.01.1 (N.O. contact)
6 STOP/SIE 01.05.01.1 (N.O. contact)
7 Reserved
SAVE 01.05.01.1
DISPLAY MAR 01.05.01.1
The 1620 debounces button presses through RC integrators
with a 3mS time constant, so 15mS is the minimum pulse width.
On a typewriter output instruction, this leaves us 7mS to
sample the magnet and assert TSC2. But wait! TSC2 goes
through its own integrator, which means that by the time
the 1620 sees it, we will have a Write Check due to
lack of Response. We'll have to try it and see. We may
have to schedule an interrupt to turn the button back off.
This is only troublesome for typewriter output. All other
I/O waits for our handshake.
CONSOLE MAR REGISTER (CMR)
This register controls the 1620 MAR DISPLAY SELECTOR function,
replacing the front panel rotary switch. It also controls
the SAVE and DISPLAY MAR buttons. I ran out of hardware,
so the interface is a bit asymmetrical.
CMR[0:3] values of 0-12 energize MAR[0...12], respectively.
MAR[1...11] go to the MAR DISPLAY SELECTOR switch positions.
MAR0 and MAR12 are spares.
CMR[0:3] = 13 or 14 is reserved.
CMR[0:3] = 15 drives the SAVE button.
Setting CMR[4] = 1 kills all of MAR[0...12] and SAVE.
This is not a feature; it's wired this way to make
board layout easier.
CMR[5] is reserved.
CMR[6] drives MAR13, a low-active spare line.
CMR[7] drives the DISPLAY MAR button.
TYPEWRITER
LPT CONTROL LINES
TEn(P1C1) Clocks P0D into the TDR on its 0-1 transition, and
into the TCR on its 1-0 transition.
TYPEWRITER CONTROL REGISTER (TCR)
Bit What
0-2 TMux[0:2] Data mux control
3 TShiftCon SHIFT CONTACT 01.82.70.1 CXB-42
4 TLC LAST COL CONTACT 01.82.70.1 CXB-41
5 TTabCon TAB INTLK CONTACT and
CARR RET INTLK CONTACT 01.82.70.1 CXB-40
6 TSC2 SELECTOR COMMON CONTACT #2 01.81.50.1 CXB-37
7 TSC1 SELECTOR COMMON CONTACT #1 and
SPACE INTERLOCK CONTACT #1 01.81.60.1 CXB-43
TMux= What
0 No typewriter data appears on P1D.
1 TMag[1:8] appear on P1D[0:7].
2 TMag[9:16] appear on P1D[0:7].
3 TMag[17:24] appear on P1D[0:7].
4 TMag[25:32] appear on P1D[0:7].
5 TMag[33:40] appear on P1D[0:7].
6 TMag[41:43] appear on P1D[0:2] and
TSpaceMag, TTabMag, TCRMag, TShiftMag, and
TStoreMag appear on P1D[3:7].
7 Reserved
TCR OUTPUTS
TShiftCon Tells the 1620 the type basket is shifted.
Assert all the time the virtual basket is shifted,
whether by the 1620 or by the user.
TLC Tells the 1620 you've hit the right margin.
Ignored except during WxTY or K.
Pulse for 100mS on last column.
TTabCon Tells the 1620 you're doing a tab or CR.
Ignored except during K.
Assert when TTabMag or TCRMag is sampled TRUE.
Negate 10mS after TTabMag/TCRMag sample FALSE.
TSC2 This contact closes on every typebar up and every space.
This contact and SPACE INTERLOCK CONTACT #2 CXB-38 are tied
together in F-level 1620s and standard 1620 typewriters.
I tied them in my B-level 1620 with no ill effect.
We drive only CXB-37 in case CXB-38 is the D. Wise
Backspace feature.
On input, make and break "inside" the make/break of TSC1.
On output, pulse for each magnet assertion; the 1620
will get a Write Check if TSC2 does not happen within
22mS of the magnet.
TSC1 This contact closes on every typebar up and every
space, PROVIDED the 1620 is doing input. Never assert it
unless TStoreMag is TRUE.
1620 Response occurs on the trailing edge of TSC1.
TSC2 must not make until +S FLAG at the 1620 is stable
or you may get a glitch on -S TPWR RESP GATE CTRL which
will cause a spurious Response. Since both contacts
feed into the 1620 electronics via identical RC integrators,
1mS is probably enough and 5mS is definitely enough.
TYPEWRITER DATA REGISTER (TDR)
Bit What
7 Drives FLAG 01.81.64.1 CXB-34.
Assert (and pulse TSC1/TSC2) when the user hits the FLAG key.
Assert 5ms before TSC2 to avoid a spurious Response.
Assert by writing 1.
6 Drives BACKSPACE 01.81.60.1 CXB-38. DO NOT USE
THIS on a standard 1620. It is applicable only to
David Wise's 1620, which has a backspace feature.
On a standard 1620 it will prematurely drive TSC2,
which will probably cause the 1620 to misinterpret
a Flag as a Flag-0 and store it.
Assert by writing 1.
5 Drives Typewriter X bit 01.81.60.1 CXB-03.
Picks a 75mA relay. Assert by writing 1.
4 Drives Typewriter O bit 01.81.60.1 CXB-05. Same.
3 Drives Typewriter 8 bit 01.81.64.1 CXB-23. Same.
2 Drives Typewriter 4 bit 01.81.62.1 CXB-16. Same.
1 Drives Typewriter 2 bit 01.81.62.1 CXB-12. Same.
0 Drives Typewriter 1 bit 01.81.62.1 CXB-10. Same.
P1D INPUTS
01.82.80.1, 01.82.82.1, 01.82.84.1, 01.82.86.1
Display the appropriate character and pulse TSC2
each time one of these samples TRUE. Note: Flag
and Centerscore don't space the carriage.
These signals are driven by relay contacts.
TRUE when you read 1.
TMag[01:08] CXA-[02:09] AZSX@CFV
TMag[09:16] CXA-[10:17] GBHN<4J><7M><5K><8,>
TMag[17:24] CXA-[18:25] <6L><9.>+/$QW
TMag[25:32] CXA-[26:33] E@R(T)Y
TMag[33:40] CXA-[34:41] <1U>=<2I><00><3O>*P
TMag[41:43] CXA-[42:44] <##>-
TShiftMag Receives SHIFT SOLENOID 01.82.70.1 CXA-47. Keep the
virtual basket shifted all the time this samples TRUE.
TTabMag Receives TAB SOLENOID 01.82.70.1 CXA-45. Tab the display
and pulse TTabCon each time this samples TRUE.
TCRMag Receives CARR RTN SOLENOID 01.82.70.1 CXA-46. CR the
display and pulse TTabCon each time this samples TRUE.
TStoreMag Receives KEYLOCK SOLENOID 01.82.72.1 CXA-48. All the
time this samples TRUE, an RxTY operation is in progress.
KEYLOCK is a misnomer; actually, it unlocks the keyboard.
ALGORITHM (Typewriter output)
(This routine is entered when any char TMag goes true)
Display char
Set TSC2
If at right margin
Set TLC
Wait 15mS
Clear TSC2
Wait for TMag[whatever] to go away
ALGORITHM (Typewriter control)
(This routine is entered when TShiftMag changes state
or TTabMag or TCRMag go true)
If TShiftMag changed
{
Switch char set
Set or Clear TShiftCon
}
If TTabMag
{
Tab the display
Set TTabCon
Wait for !TTabMag
}
If TCRmag
{
CR the display
Clear TLC
Set TTabCon
Wait for !TCRMag
}
ALGORITHM (Typewriter input)
(This routine is entered when TStoreMag goes true)
While TStoreMag
{
Run Typewriter Control algorithm for shift
Wait for key or !TStoreMag ; !TStoreMag aborts
Set TDR
Set TSC1
Wait 5mS
Set TSC2
Wait 15mS
Clear TSC2
Wait 5mS
Clear TSC1
Clear TDR
}
MONITOR (Driving a real 1621)
LPT CONTROL LINES
MonEn(P0C2) Clocks P0D into the MDR on its 0-1 transition,
and into the MCR on its 1-0 transition.
MONITOR DATA REGISTER (MDR)
Bit What
0 Punch 1
1 Punch 2
2 Punch 4
3 Punch 8
4 Punch C
5 Punch O
6 Punch X
7 Punch EL
MONITOR CONTROL REGISTER (MCR)
Bit What
0 Mon_PNoFeed
1 Mon_PFeed
2 Mon_RClutch
6 SMux (Mon_S[0:7] -> P1D)
7 DMux (Mon_R[0:7] -> P1D)
P1D INPUTS
Mon_R[0:7] Receives +S TAPE LEVEL [1:8] 01.83.20.1 MONSC-[11:18]
from the 1621. Sample on the trailing edge of Mon_RSync.
These signals are gated onto P1D by DMux in the MCR.
TRUE when you read 0.
Mon_S[0:7] Receives various status signals from the 1621.
These signals are gated onto P1D by SMux in the MCR.
Bit TRUE= Receives IBM Name
0 Reserved
1 0 Mon_NonProcRun +S NON PROC RUNOUT 01.83.60.1 MONSC-20
2 Reserved
3 1 Mon_PRdy +S TAPE TENSION CONT 01.84.10.1 MONSC-23
4 0 Mon_P3 +S P3 RESPONSE 01.80.30.1 MONSC-24
5 0 Mon_PCheck +S PUNCH CHECK 01.81.45.1 MONSC-25
6 0 Mon_PFeedSw +S TAPE FEED 01.84.10.1 MONSC-27
7 0 Mon_P1 +S PCB1 01.80.25.1 MONSC-28
LPT STATUS LINES
Mon_RSync Receives +S TAPE SYNC EXIT 02.??.??.? MONSC-19.
This signal will pulse at 150 Hz all the time Mon_RClutch is true.
If Mon_RRdy is TRUE, store Mon_R[0:7] on Mon_RSync's trailing edge.
Mon_RRdy Receives -S READER RDY 02.83.60.1 MONSC-22.
Clear Mon_RClutch IMMEDIATELY if this goes false.
ALGORITHM (Offline Punching)
While there is data to punch
{
Wait for Mon_P1 ; End of previous punch
Set MDR and Mon_Pfeed ; Cmd+Data for this punch
Wait for Mon_P3 ; Mon_PCheck is valid
If Mon_Pcheck ; Parity error at punch
{
Keep current MDR
Clear Mon_PFeed ; STOP!
Set Mon_PNoFeed ; Don't advance tape
Wait for Mon_P1 ; End of cycle
Clear Mon_PNoFeed ; It's done its job
Notify user
Wait for PFeedSw or abort
Set MDR = 0x7F ; Tape Feed code
Set Mon_PFeed
Wait for !Mon_PFeedSw
Clear Mon_PFeed
Wait for Mon_P1
Wait for user resume
}
}
Clear Mon_PFeed
ALGORITHM (Offline Reading)
While Mon_RRdy
{
Set Mon_RClutch
Set DMux
Wait for Mon_RSync
Wait for !Mon_RSync
Store P1D
}
For realtime archiving, we forward as quickly as possible
all signals from 1621 to 1620 and vice versa.
The most critical timing is from Mon_RSync falling edge to
1620 RClutch falling edge to Mon_RClutch falling edge.
If there is a delay here, the 1621 will advance past the next
character before stopping. We probably have to disable
interrupts for the 75uS following !Mon_RSync.
PAPER TAPE (Emulating a 1621)
LPT CONTROL LINES
RSync Drives +S TAPE SYNC EXIT 01.80.30.1 SCA-19, whose trailing
edge causes a Response. Ignored except during RxPT.
PEn(P0C1) Clocks P0D into the PDR on its 0-1 transition, and
into the PCR on its 1-0 transition.
PAPER TAPE CONTROL REGISTER (PCR)
Bit What Assert by writing:
0 P4 1
1 P2 1
2 RRdy 1
3 PRdy 1
4 PCheck 0
5 PFeedSw 1
6 P1 0
7 P3 1
PCR OUTPUTS
P4 Powers the PNoFeed receiver pullup.
P4 must be TRUE during P3 to sample PNoFeed. A reasonable
approach is to imitate the 1624's PCB4 timing, which
surrounds PCB3 but does not overlap PCB1 or PCB2.
P2 Powers the P[0:7] and PFeed receiver pullups.
In order to clear the 1620 SCRs driving P[0:7] and PFeed,
P2 must be FALSE during the 1620 Response that occurs when
P1 goes TRUE. A reasonable approach is to imitate the 1624's
PCB2 timing, which is like PCB1 but lags slightly behind.
RRdy Drives -S READER RDY 01.83.10.1 SCA-22.
Negate at EOF on the source paper tape image file.
PRdy Drives +S TAPE TENSION CONT 01.84.10.1 SCA-23.
Negate if unable to write to the sink paper tape image file.
PCheck Drives +S PUNCH CHECK 01.81.45.1 SCA-25.
Ignored except during P3.
Assert at P3 if P[0:7] have even parity.
PFeedSw Drives +S TAPE FEED 01.84.10.1 SCA-27.
Assert all the time the user presses the PUNCH TAPE FEED key.
P1 Drives +S PCB 1 01.80.25.1 SCA-28.
Ignored except during WxPT.
Causes Response (if Response Gate is set) or
Disconnect (if Disconnect Gate is set).
Negate every time PFeed samples TRUE.
If PFeed samples FALSE after P2, leave P1 and P2 asserted.
P3 Drives +S P3 RESPONSE 01.80.30.1 SCA-24.
Ignored except during WxPT.
Pulse while P1 is FALSE to set the Response Gate.
To avoid a hazard, the pulse must not overlap P1.
PDR OUTPUTS
R[0:7] Drives +S TAPE LEVEL [1:8] 01.83.20.1 SCA-[11:18].
Ignored except during RxPT.
Assert by writing 0.
P1D INPUTS
P[0:7] Receives -N PUNCH {1,2,4,8,C,O,X,EL} BIT
01.84.20.1 SCA-[87652431].
These receivers contain pullups which are powered by P2.
When P2 is TRUE, P[0:7] is gated onto P1D[0:7].
Sample before PCB3.
TRUE when you read 0.
LPT STATUS LINES
RClutch Receives +S CLUTCH DRIVE 01.83.10.1 SCA-21.
Transmit data on R[0:7] and pulse RSync
all the time this samples TRUE.
PFeed Receives -N PUNCH FEED 01.84.10.1 SCA-9. Store punch data from
P[0:7] and negate P1 every time this samples TRUE.
This receiver contains a pullup which is powered by P2.
PNoFeed Receives -N PUNCH NO FEED P 01.84.10.1 SCA-10.
Don't store most recent punch data when sampled TRUE.
The receiver contains a pullup which is powered by P4.
Sample during P3.
ALGORITHM (Paper Tape board presence detect)
(Entered with all mux sources off)
If P1D != 0
Error
Set P2 ; Energize punch pullups/data source
If P1D == FF ; Pulled high by P2
Board is present
Else If P1D == 0
Board is absent
Else
Error
ALGORITHM (Emulate paper tape punch)
(When idle, P1 and P2 are true, P3 and P4 false)
(If unable to write to paper tape sink file, clear PRdy)
(This routine is entered when PFeed goes true)
Wait 45-60uS ; Wait for first mem cycle
While (PFeed)
{
Read P1D
Clear P1
Clear P2 ; Drop Data/Feed pullups
Set P4 ; Enable NoFeed pullup
Set P3 ; Set Response Gate
If parity of read byte is even
Set P_Check
Wait 15-30uS ; For 1620 Tpd(Check-NoFeed)
If !PNoFeed
Store byte
Clear P3
Clear P4 ; Drop NoFeed pullup
Set P1 ; Cause Response
Wait 45-60uS ; Wait for mem cycle
Set P2 ; Enable Data/Feed pullups
Wait 15-30uS ; Receiver settling time
}
ALGORITHM (Emulate reader)
(If unable to read from paper tape source file, clear RRdy)
(This routine is entered when RClutch goes true)
Wait 0-15uS
While (RClutch)
{
Set PDR
Set RSync
Wait 15uS ; Deliver a noticeable pulse
Clear RSync ; Cause Response
Wait 90uS ; For 1620 to maybe drop RClutch
}
TIMING
The 1620 stops at W5 if the Hold trigger is on. The Sync trigger
resumes it by clearing the Hold trigger.
A and B refer to the A ADV W6-D2 and B ADV W6-D2 timing pulses.
The 1620 clears the Sync trigger at R2-D3 in Trigger 30.
CARD READ
A HOLD B 31 A 30 B 31+HOLD A 30 B ...
Sync and Sample Timing
SET MDR SAM I/O is T5-D3 in Trigger 30.
Data setup time from CDR to 1620 MDR is 20uS.
After each Sample, the 1622 asserts CD RD SYNC at R4-D8 to
indicate that the next character is ready.
CD RD SYNC turns on the Sync trigger which prevents the Hold
trigger from getting set at Trigger 31 entry.
The 1620 determines the Sync to Sample delay. >= 6uS.
The PC determines CDR valid to Sync delay. >= 15uS.
Therefore data is always available at least 21uS before Sample,
which just meets the setup time. If we were 1uS later, 15uS
delay wouldn't be enough and we would have to wait 30.
Since the PC may be interrupted at any time for an unpredictable
period, we cannot assume that we have kept the 1620 running.
On all transfers except the first, if the 1620 pauses, it does so
just before Trigger 30, so to avoid a runon, the sync pulse
must end by R2, which requires that Tpw(CD RD SYNC) <= 9uS.
There's no lower limit. 10K+.001 on a 74LS123 yields a 3.5uS pulse.
Assuming (a) no PC interrupts, (b) we let the 1620 stop during
the intro, (c) the PC timer is exactly 15uS, (d) the 1620 oscillator
is exactly 1uS, and (e) we start on a PC timing boundary,
here's the timing in uS. If the PC is slower, sync will get later
and later and the 1620 will occasionally pause and resume.
Each resume will look like the middle "30" below.
If the PC is faster, it will wait slightly longer for Sample.
Write to CDR
Wait 15-30uS
Sync
Wait for Sample
LEGEND: |= 1620 stopped
/= 1620 cycle boundary
^= Sync
,= PC timing boundary
W= PC writes to CDR
*= Sample
| ,W^/15,5/6*W4,10/5,^15,/6*W9,5/10,^10/5,1*W14/,^15,5/ ...
H... 31 30 31+H 30 31+H 30 31+H Repeat----|
^--------------------------------------------------|
|
Disconnect Timing
The 1620 ignores CD RD DISCONNECT except during Trigger 30.
The signal that sets the Rd Check trigger is gated with RW CALL
and SET MDR SAM I/O.
The RW Call trigger is cleared by CD RD DISCONNECT.
This means that if we Disconnect before Sample, if the last character
was bad the 1620 won't notice. If we Disconnect after Trigger 30,
the 1620 will continue transferring.
Therefore, Disconnect needs hardware assistance, a flip-flop clocked
by Sample, to guarantee that the pulse starts inside the window.
It doesn't matter when it ends, because the 1620 will not reach
the first Trigger 30 of the next card until we tell it to (via Sync).
CARD WRITE/DUMP
A 8+HOLD B 8 A 30 B HOLD A 30 ...
Sync and Sample Timing
The 1620 runs a memory cycle in Trigger 30 (data in the MDR
at R1) and asserts SET I/O SAM MDR at T3-D7 during the following
Hold trigger time. Sample comes 17uS after MDR valid, which is
too short for it to propagate through the output translator.
The 1622 gates data into the Single Character Register at R0-D4 and
asserts CD PUNCH SYNC at R1-D8 during Hold time. This is 3 uS after
Sample, giving a total Tdav = 20uS.
Since we can't wait 3uS we'll wait 15-30uS, which locks us into
a 45uS cycle where the 1620 pauses at W5 (10uS after data arrives at
our end) and we read and Sync 5uS after that.
Sync
Wait for Sample
Wait 15-30uS
Read
| ,^/15,5/10,10/3*2,15|,R^/15,5/3*7,10|5,R^/15,5 ...
8+H... 8 30 H 30 H Repeat----\
^-------------------------/
Disconnect Timing
As with Read, we must not Disconnect before the final Sample lest we
prevent Write Check if the last character has bad parity. During
Read, the 1622 drops Disconnect at Exit, but for Write, the 1622
ignores Exit and simply pulses Disconnect for 14uS. The timing is
unimportant except for the minimum on the leading edge, because the
1620 watches Punch Disconnect all the time. Disconnect does not
always cause Exit (a 20k Dump Numerical will punch 250 cards in a row)
so like the 1622 we don't watch for Exit but just go back to being
Ready, which in the 1620 enables Punch Data Gate.
ISSUES
Does CD RD BUFF READY control anything besides the Reader No Feed lamp
and CD RD DATA GATE? Better not.
Does CD PUNCH BUFF READY control anything besides the Punch No Feed
lamp and CD PUNCH DATA GATE? Better not.
TYPEWRITER OUTPUT
We have no control over the magnet timing; it comes from the cam
in Gate C, 10 chars per second. We don't pulse TSC1, because
in a real typewriter, it's powered by a relay that's only picked
during input.
The magnet is energized for 22mS. We must make TSC2 somewhere in
that window to avoid a Response Check error. Since TSC2 goes through
an RC integrator with 3mS time constant, possibly up to the first
15mS is wasted there, leaving us 7mS to respond. This is still
plenty of time.
Magnet 0000011111111XXXXXXXXXXXXXXXXX000000
TSC2 000000000000000011111000000000000000
Read Data ^
TYPEWRITER CONTROL
This is only necessary to unlatch some relays that were set up when
TTabMag was asserted. It doesn't affect the cpu except it notices
when the op is done and goes on.
TTabMag 000001111111111111111111100000000000
TTabCon 000000001111111111111111111100000000
Op Done ^
TYPEWRITER INPUT
We stay in this mode all the time the Store Magnet is picked.
Our speed is limited by the relays.
The data goes away as soon as Selector Common 1 drops,
but the 1620 grabs it before the relays have time to drop out.
Data 000000111111111111111000000000000000
SC1 000000111111111111111000000000000000
SC2 000000000001111000000000000000000000
Response ^-.
Rsp Gate ^----------.
READER INPUT
The cpu engages the reader clutch, and the reader outputs
sync pulses.
The Sync trailing edge causes a Response, which lights Trigger 31,
then Trigger 30, then the Hold trigger. Then we can do another,
so the minimum cycle time is 60uS. Since we don't know whose
1uS period is faster, the absolute minimum is 75uS.
Since the first trigger is 31 which doesn't do anything,
the data setup time before Response is 0uS. The hold time
after Response is 40uS.
Normally, the 1620 negates RClutch a few gate delays after the
RSync trailing edge on EOL, which gives us almost 75uS to
sense it, but if the user hits SCE, RClutch stays on until
W5+Hold, 60uS later than normal. A 75uS cycle leaves us 15uS - gate
delays - LPT cable charge time, which is probably not enough.
Clutch 00000111111111111111111111111000000
data xxxxxx1111122222333334444455555xxxx
Sync 00000111001110011100111001110000000
Response ^-. ^-. ^-. ^-. ^-.
PUNCH OUTPUT
'--' denotes the time when the PFeed pullup is dead.
P1 causes Response/Disconnect.
Initial data is available as soon as PFeed goes true.
Subsequent bytes are available 60uS after P1 leading edge.
PFeed goes false 40uS after P1 if the data was RM or if
SCE was used. I have not analyzed DNPT's 19999 stop.
The speed will probably be limited mostly by cable capacitance.
PFeed 00111111-----111-----111-----000000
P1 11111110000011100000111000001111111
P2 11111111000001110000011100000111111
P4 00000000111100001111000011110000000
P3 00000000011000000110000001100000000
Read data ^ ^ ^
Response ^. ^. ^.
Rsp Gate ^---. ^---.
Disconn ^