Title
Simulation speed and logic design
Catalog Number
102624716
Type
Moving Image
Description
Logic design has become more formalized over the last several years due to the increasing complexity of the circuits being designed. A result has been an increased need for logic simulation at the level of the design by using a hardware description language to express the design. This need for simulation capability has put a great emphasis on execution speed of HDL simulators. This lecture describes the need for large amounts of simulation and techniques which can be used to implement a fast simulator. Examples are taken from Chronologic Simulation's VCS Verilog compiler."
Date
1993-09-09
Credits
Sanguinetti, John
Publisher
University Video Communications
Duration
00:49:00
Format
Betacam SP
Copyright Holder
Computer History Museum
Category
Lecture
Series Title
University Video Communications: Distinguished Lectures
Credit
Gift of University Video Communications
