Title
Greene patent notebook (#454)Catalog Number
102722962Type
DocumentDescription
Describes testing of devices for use in ferrite core memory systems. Evaluation of core output vs. drive, detector circuits, and core switching inductance. Compares core vs. thin-film vs. semiconductor technologies for storage. A demonstration system for bipolar 256-bit IC memory chips (possibly a predecessor to the Illiac IV project) and a proposed bipolar memory cell design (p. 142). .Date
1965-09-08-1970-06-18Author
Greene, Frank S., Jr.Biographical Notes
Frank S. Greene attended Washington University in St. Louis where he obtained a B.S.E.E. He earned an M.S. in electrical engineering at Purdue University and a Ph.D. at Santa Clara University in 1970. He joined the Fairchild Memory Products Division as a junior engineer in Harley Perkins’ Ferrite Core Memory Group in 1965. By 1968 this activity was closed and Greene worked in a Flat-Wire Memory section managed by C. Bittmann in the Physics Department. In 1970-71 he worked with Wendell Sander on the Illiac IV semiconductor memory system project. In the early1970s, he co-founded software and computer service companies Technology Development Corp. and ZeroOne Systems Inc. Greene was among the first black students to attend college at Washington University and an early African-American engineer in Silicon Valley. He founded NewVista Capital, a venture capital firm with a special focus on minority and female-headed firms.Publisher
Fairchild SemiconductorIdentifying Numbers
| Document number | 454 |
Extent
Approximately 56 dated entries over 146 pages.Dimensions
12 x 10 inchesPatents
The author is named as inventor on 1 U.S patent. This patent was assigned to Fairchild:U.S. patent 3654610, “Use of faulty storage circuits by position coding.” Filed 1970-09-28. Issued 1972-04-04.
Category
NotebooksCollection Title
Fairchild Semiconductor notebooks and technical papersPublications
The author contributed to the following R&D Technical Reports (TR) and papers in professional publications during his service at Fairchild:TR 357 Combinatorial decoding of semiconductor memory arrays (1968-09-06).
TR 394 LSI bipolar memory for symbol II (1969-03-20).
Rice, R., Sander, W.B., Jr. and Greene, F.S. Design considerations leading to the ILLIAC IV LSI process element memories. IEEE Journal of Solid-State Circuits, vol. 5, iss. 5 (1970): 174-181.