This volume contains gate design evaluation studies and suggestions for improved CTL (Complementary Transistor Logic) cell designs, including design, test and measurement data for 9820 and 9821 Line Driver devices (p. 7); proposal for clamped input cell (witnessed by R. Marley and R. Badertscher p. 47); zener diode clamp (p. 49); and NPN replacement for PNP in CTL gate (p. 51).
Parkinson, Ward D.
Ward D. Parkinson was raised in Blackfoot, Idaho. He received a B.S.E.E. from Utah State University, M.S.E.E. from Stanford University and a J.D. from Chicago-Kent College of Law, Illinois Institute of Technology. He joined Fairchild circa 1971where, supervised by Robert Marley, he designed high-speed ECL logic and memory circuits. He worked for Motorola in Phoenix, Arizona, and start-up Inmos Ltd. in the mid-1970s before co-founding Micron Technology, Inc. in Boise, Idaho, with his twin brother Joseph L. Parkinson in 1978. Micron became a leader in the production of high-density MOS memory chips beginning with the 64K DRAM. He served as Chairman and CEO of Micron from 1978 through 1986 and as Vice Chairman until 1989. He serves on the boards of Blue Cross of Idaho, Chicago Kent Law School, and the engineering board of Utah State University.
6 dated entries over 53 pages.
12 x 10 inches
The author is named as inventor on more than 30 U.S patents assigned to Motorola, Mostek, Intel, Micron and Ovonyx. None are assigned to Fairchild.
Fairchild Semiconductor notebooks and technical papers