Artifact Details


Schroeder patent notebook (#338)

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Describes experiments and results on a varied range of wafer fabrication processes including etching, diffusion, oxidation, epitaxial growth and dielectric isolation. This volume is densely filled with text and cross section diagrams. Topics include SCR development (p. 64); idea for oxide isolation of transistors and press cutting of similar work at Radiation Inc. (p. 74); photo of R. Bohn’s dielectrically isolated CMA device; mesa isolated diode technique (p. 104); and description of a diode matrix to form a seven segment numerical readout display in a DIP package (p. 106).




Schroeder, Jon Murray

Biographical Notes

Jon Murray Schroeder joined Fairchild in 1963 and worked as a research engineer on a wide variety of wafer fabrication processes including etching, diffusion, oxidation, epitaxial growth, and dielectric isolation. A 1966 R&D organization chart lists him as a Senior Engineer in the Technology Development Section reporting to C. Plough. He also worked with John Schmidt in the Fairchild Memory Products business unit on a project to attach multiple chips to a ceramic substrate to form a 1024-bit hybrid memory called Semiconductor Advanced Memory (SAM). Together with Schmidt he co-founded Computer Microtechnology Inc. (CMI) in 1968 to build memory products. In the early 1980s, he applied for patents assigned to Indy Electronics Inc. an integrated circuit assembly and packaging company located in Manteca, California, in the early 1980s.


Fairchild Semiconductor

Identifying Numbers

Document number 338


101 dated entries over 113 pages.


12 x 10 inches


The author is named as inventor on 17 U.S patents, including 5 patents assigned to Fairchild:

U.S. patent 3639811, “Semiconductor with bonded electrical contact.” Filed 1970-11-19. Issued 1972-02-01.

U.S. patent 3606679, “Method for interconnecting solid state devices such as integrated circuit chips.” Filed 1969-10-29. Issued 1971-09-21.

U.S. patent 3509433, “Contacts for buried layer in a dielectrically isolated semiconductor pocket.” Filed 1967-05-01. Issued 1970-04-28.

U.S. patent 3489961, “Mesa etching for isolation of functional elements in integrated circuits.” Filed 1966-09-29. Issued 1970-01-13.

U.S. patent 3550261, “Method of bonding and an electrical contact construction.” Filed 1967-11-13. Issued 1970-12-29.



Collection Title

Fairchild Semiconductor notebooks and technical papers


The author contributed to the following R&D Technical Reports (TR) and papers in professional publications during his service at Fairchild:

TR203 In-furnace etching of silicon prior to oxidation (1965-03-17).

Dumesnil, M. and Schroeder, J. A large-scale integration hybrid substrate. 1969 IEEE International Solid-State Circuits Conference: Digest of Technical Papers, vol. XII, (1969): 66-67.


Gift of Texas Instruments Incorporated

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