TitleEarly patent notebook (#3191)
DescriptionDescribes two circuit configurations for use in VLSI complexity devices. The entry dated 1987-04-27 begins, “At about 3AM this morning, it occurred to me that in the S2I2 patent (U.S. patent 4629912 - below) we had neglected a claim …” The entry dated 1987-06-16 entitled “New VLSI Logic” includes text and schematics for a low power CCL gate.
AuthorEarly, James M.
Biographical NotesJames M. Early was born in 1922 in Syracuse, New York. He received a B.S. in Pulp and Paper Manufacturing from the New York State College of Forestry, Syracuse in 1943. After army service at Ohio State University and the Manhattan Engineer District, Oak Ridge, Tennessee, he returned to O.S.U. as a graduate student and instructor in Electrical Engineering. He received the M.S. (magnetron resonances) in 1948 and the Ph.D. (anisotropic dielectric waveguides) in 1951. Early joined Bell Laboratories in 1951 and during his eighteen years at Bell, he created much of the design theory of bipolar transistors, discovered the effects of space-charge layer widening (the "Early effect"), created the oscillator transistor for the first U.S. satellite, led development of solar cells and transistors for Telstar I, and the development of sealed junction technology as part of Bell Lab's first major IC program. He ended his Bell Labs service as Director of the Electron Device Laboratory at Allentown, Pennsylvania. In September 1969 he joined Fairchild to replace Gordon Moore as Director of the R & D Lab, later known as the Fairchild Research Center. During his tenure, Fairchild created the Isoplanar bipolar process and the first Isoplanar memory products, buried channel CCD imagers, and the 100K series ECL family for high-speed computers. Under his leadership Fairchild installed the first ion implanter in a merchant semiconductor company (1970) and the first commercial electron beam mask-making machine (MEBES 1 - 1977). He became a technical adviser in mid-1983 and retired from Fairchild at the end of 1986. He died in 2004.
Extent2 dated entries over 17 pages.
Dimensions12 x 10 inches
PatentsThe author is named as inventor on 14 U.S patents, including 10 patents assigned to Fairchild:
U.S. patent 4629912, “Schottky shunt integrated injection.” Filed 1985-09-16. Issued 1986-12-16.
U.S. patent 3806772, “Charge coupled amplifier.” Filed 1972-02-07. Issued 1974-04-02.
U.S. patent 3896485, “Charge-coupled device with overflow.” Filed 1973-12-03. Issued 1975-07-02.
U.S. patent 3955101, “Dynamic reference voltage generator.” Filed 1974-07-29. Issued 1976-05-04.
U.S. patent 3999082, “Charge coupled amplifier.” Filed 1974. Issued 1976-12-21.
U.S. patent 4593303, “Self-aligned antiblooming structure for charge-coupled devices.” Filed 1985-07-23. Issued 1986-06-03.
U.S. patent 4833521, “Means for reducing signal propagation losses in very large scale integrated circuits.” Filed 1988-07-08. Issued 1989-05-23.
U.S. patent 5118631, “Self-aligned antiblooming structure for charge-coupled devices and method of fabrication.” Filed 1989-08-03. Issued 1992-06-02.
U.S. patent 4583111, “Integrated circuit chip wiring arrangement providing reduced circuit inductance.” Filed 1983-09-09. Issued 1986-04-15.
U.S. patent 4839717, “Ceramic package for high frequency semiconductor devices.” Filed 1988-06-07. Issued 1989-06-13.
Collection TitleFairchild Semiconductor notebooks and technical papers
PublicationsThe author contributed to the following R&D Technical Reports (TR) and papers in professional publications during his service at Fairchild:
Early, J. M., Classic semiconductor devices-point contact through HSI; solving easy problems: part II. 50th Annual 1992 Device Research Conference Digest, (1992): 0_14 - 0_15.
Guidry, M., Amelio, G. and Early, J., A sense amplifier for a low clock capacitance 16K CCD memory. 1976 IEEE International Solid-State Circuits Conference: Digest of Technical Papers, vol. XIX (1976): 190-191.
Shoucair, F. S. and Early, J. M., High-temperature diffusion leakage-current-dependent MOSFET small-signal conductance. IEEE Transactions on Electron Devices, vol. 31, iss. 12 (1984): 1866-1872.
Varshney, R. C., Guidry, M. R., Amelio, G. F. and Early, J. M., A byte organized NMOS/CCD memory with dynamic refresh logic, IEEE Journal of Solid-State Circuits, vol. 11, iss. 1 (1976): 18-24.