TitleRice patent notebook (#1539)
DescriptionThis volume contains ideas for in-system repair of malfunctioning components with several entries written by Richard Bechtel and witnessed by the author; Rice Data Base Array Lock Step processor; correction technique for hard and soft failures in memory systems; and pasted-in pages illustrating use of Rice Correction algorithm.
This is one of 4 patent books authored by Rice. The other volumes are numbered 307, 429, and 1378.
Biographical NotesRex Rice was born in Douglas, Arizona, and graduated from Stanford University in 1940 with a degree in mechanical engineering. He joined Douglas Aircraft and later Northrup Aircraft and conducted research in stress analysis of sloped-wing design. In 1955, Rice joined the IBM Research Laboratory in Poughkeepsie, New York, where he took part in the development of the first fully transistorized digital calculator. His expertise in high-level language computing led him to join the Fairchild Semiconductor R&D Laboratory, Palo Alto circa 1963 to establish a department to investigate opportunities for ICs in digital system applications. He proposed many improved packaging designs and co-invented the dual-in-line package with Bryant “Buck” Rogers and Don Forbes. In 1966 he was listed on the R&D Professional Staff organizational chart as Manager of the Digital Systems Research Department reporting to Gordon Moore. Rice led the development of the SYMBOL computer and in 1970 the semiconductor memory system for the Illiac IV computer. Later, Rice held successive engineering management positions at the Fairchild Systems Technology Division, including Director of Technology, Manager – Multi-chip Memories, Director of Memory Systems Operations, and Director of Advanced Systems Development, He retired from Fairchild to become a consulting engineer in 1980. Engineers (IEEE).
ExtentApproximately 15 dated entries over 57 pages.
Dimensions12 x 10 inches
PatentsThe author is named as inventor on 16 U.S patents, including 5 patents assigned to Fairchild:
U.S. patent 3577130, “Means for limiting field length of computed data.” Filed 1969-10-03. Issued 1971-05-04.
U.S. patent 3643225, “Memory control system.” Filed 1969-04-02. Issued 1972-02-01.
U.S. patent 3643227, “Job flow and multiprocessor operation control system.” Filed 1969-09-15. Issued 1972-02-05.
U.S. patent 3647348, “Hardware-oriented paging control system.” Filed 1970-01-19. Issued 1972-03-07.
U.S. patent 4365332, “Method and circuitry for correcting errors in recirculating memories.” Filed 1980-11-03. Issued 1982-12-21.
Collection TitleFairchild Semiconductor notebooks and technical papers
PublicationsThe author contributed to the following papers in professional publications during his service at Fairchild:
Rice, R. The chief architect's reflections on symbol IIR. Computer, vol. 14, iss. 7 (1981): 49-54.
Rice, R. Impact of arrays on digital systems. IEEE Journal of Solid-State Circuits, vol. 2, iss. 4 (1967): 148-155.
Rice, R. LSI - Impact on digital systems. 1967 IEEE International Solid-State Circuits Conference: Digest of Technical Papers, vol. X (1967): 34-35.
Rice, R. Modular bipolar LSI memory systems. IEEE Transactions on Magnetics, vol. 6, iss. 3 (1970): 591.
Rice, R. Systematic procedures for digital system realization from logic design to production. Proceedings of the IEEE, vol. 52, iss. 12 (1964): 1691-1702.
Rice, R. A system designer views "Micro-integrated electronics." IRE Transactions on Electron Devices, vol. 8, iss. 5 (1961): 421.
Rice, R., Sander, W.B., Jr. and Greene, F.S. Design considerations leading to the ILLIAC IV LSI process element memories. IEEE Journal of Solid-State Circuits, vol. 5, iss. 5 (1970): 174-181.