Title
Western Research Laboratory technical notes TN-2 - TN-50Catalog Number
102737737Type
DocumentDescription
This box contains the following technical reports, filed in the same order as this list:Available instruction-level parallelism for superscalar and superpipelined machines
Unified vector/scalar floating-point architecture
TCP/IP PrintServer : print server protocol
TCPI/P PrintServer : server architecture and implementation
Architectural and organizational tradeoffs in the design of the MultiTitan CPU
Why aren’t operating systems getting faster as fast as hardware?
Mostly-copying garbage collection picks up generations and C++
Limits of instruction-level parallelism
Effect of context switches on cache performance
MTOOL a method for detecting memory bottlenecks
Predicting program behavior using real or estimated profiles
Electrical evaluation of the BIPS-0 package
Transparent controls for interactive graphics
I/O component characterization for I/O cache designs by Kathy J. Richardson
Attribute caches by Kathy J. Richardson and Michael J. Flynn
Operating systems support for busy Internet servers by Jeffrey C. Mogul
Predictability of libraries by Brad Calder, Dirk Grunwald, and Amitabh Srivastava