Computer History Museum

Identification sketch of chips representing the increase in bipolar integrated circuit complexity

In 1968 Gordon Moore asked Harry Sello, who worked for him in the Palo Alto R & D Laboratory of Fairchild Semiconductor, to photograph a selection of devices that illustrated his observation of the increasing number of transistors that were being fabricated on a silicon chip every year. The resulting image is posted on the Silicon Engine online exhibit at: http://www.computerhistory.org/siliconengine/moores-law-predicts-the-future-of-integrated-circuits/ Either Harry or Gordon made this sketch to identify the devices in the image. The device type and approximate transistor count for each is as follows: Upper Row (L to R): 2N697 planar transistor (1960) - 1 component (1 Tx); Micrologic Type G 3-input RTL Gate (1962) - 7 components (3 Tx + 4 R); Micrologic Type R RTL Half-Shift Register (late 1962) - 20 components (8 Tx + 12R): 945 DTL R-S flip-flop (early 1964) – 33 components (13 Tx + 21R) Lower Row (L to R): 958 Micrologic RTL Decade Counter (late 1964) – 58 components (33 Tx + 25R); 9300 TTL Universal shift register (1966) – 125 components (85 Tx + 40R); 4500 Micromatrix 32-gate DTL array (1967) – 264 components (200 Tx + 64R)

Item Details

Date
ca. 1968 (Made)
Type
Document
Catalogue number
102783359
Category
Paper/Record
Credit line
Gift of Sheila Sello
Extent
1 p.
Language
English
Acquisition number
X8761.2019
Archive collection
Harry Sello papers
Archive hierarchy
Harry Sello papers