Title
Beeson laboratory notebook (#1)Catalog Number
102722929Type
DocumentDescription
This lab notebook is described by the author as a supplement to his patent notebooks. It contains brief notes on testing and associated results. Page 47 includes further exploration of the TTL circuit disclosed in Beeson (146).Date
1960-09-08-1961-06-07Author
Beeson, R.H.Biographical Notes
R.H. Beeson joined Fairchild circa mid-1958 and remained at least until mid-1961. He worked for Vic Grinich on the application of transistors for high-speed switching in logic applications. He independently invented the Transistor Transistor Logic (TTL) logic configuration that was described in the 1962 ISSCC paper “New Forms of All-Transistor Logic” co-authored with H. W. Ruegg. Commercialized by Sylvania and copied and successfully promoted by Texas Instruments, TTL formed the workhorse digital IC family of the 1970s. In the late 1960s he was working for Amelco Semiconductor.Publisher
Fairchild SemiconductorIdentifying Numbers
Document number | 1 |
Extent
25 dated entries over 69 pages.Dimensions
10 x 8 inchesCategory
NotebooksCollection Title
Fairchild Semiconductor notebooks and technical papersPublications
The author contributed to the following R&D Technical Reports (TR) and papers in professional publications during his service at Fairchild:TR33 Short report on avalanche switching of standard and epitaxial FT-1340’s utilizing modified collector triggering (1961-01-16).
Allison, D., Beeson, R. and Shultz, R., KMC planar transistors in microwatt logic circuitry . 1961 IEEE International Solid-State Circuits Conference: Digest of Technical Papers, vol. IV (1961): 62 – 63.
Beeson, R. H., Haas, I. and Grinich, V. H., Thermal response of transistors in the avalanche mode. National Electronics Conference, 1959-10-12-1959-10-14. (Reprinted as Fairchild TP-6)
Beeson, R. and Ruegg, H., New forms of all-transistor logic. 1962 IEEE International Solid-State Circuits Conference: Digest of Technical Papers. vol. V (1962): 10-11.
Maxwell, D. A., Beeson, R. H. and Allison, D. F., The minimization of parasitics in integrated circuits by dielectric isolation. IEEE Transactions on Electron Devices, vol. 12, iss. 1 (1965): 20-25.