TitleChou laboratory notebook (Ion implantation system)
Biographical NotesSunlin Chou was born in Singapore and received B.S., M.S., and E.E. degrees from MIT in 1966, 1967, and 1968 respectively, all in electrical engineering. He joined Fairchild in 1968 where he worked on the development of a lateral PNP transistor and was involved in the set-up and operation of an ion implantation system while also earning a Ph.D. from Stanford University (1971). He moved to Intel Corporation in 1971, and worked on device modeling, memory design, and process development projects, before assuming responsibility for Intel’s DRAM process technology development effort. He was senior vice president and general manager of Intel’s Technology and Manufacturing Group when he retired in 2005. He was awarded the IEEE Robert Noyce Award in 2013.
ExtentApproximately 70 dated entries over 196 pages.
Dimensions10 x 8 inches
DescriptionThis Volume I of a record of activities, together with names of vendors, etc., involved in the setting up and acceptance testing of ion implantation equipment. In succeeding years, ion implantation replaced high-temperature diffusion as a means of introducing desired impurities into silicon wafers with improved control of device characteristics. Specific entries include a photograph of LS-4 High Voltage Terminal system (p. 4) and of LS-5 system (P. 50); description of a system offered by Ion Equipment Corporation, Santa Clara, California, and the business card of the president, Ralph L. Vaerst. (p 34). Vaerst is the person credited with suggesting that Don Hoefler use the name Silicon Valley in his first published use of the name in Electronic News in January 1971.
Collection TitleFairchild Semiconductor notebooks and technical papers
PublicationsThe author contributed to the following R&D Technical Reports (TR) and papers in professional publications during his service at Fairchild:
TR430 An investigation of lateral transistors I. DC characteristics [1968-9-10-06].
TR446 On the measurement of recombination currents in epitaxial base transistors [1969-12-12].
TR464 A study of diffused layers of arsenic and antimony in silicon using the ion scattering technique [1970-05-22].
TR504 An investigation of lateral transistors II - small signal characteristics [1971-03-26].
*S. Chou. An investigation of lateral transistors - D.C. characteristics . Solid-State Electronics, vol. 14, iss. 9 (1971-09): 811–826.
*S. Chou. Small-signal characteristics of lateral transistors . Solid-State Electronics, vol. 15, iss. 1 (1972-01): 27–38.
*S. Chou, L. A. Davidson, and J. F. Gibbons. A study of diffused layers of arsenic and antimony in silicon using the ion-scattering technique. Applied Physics Letters, vol. 17, iss. 1 (1970-07): 23.
* This paper is included in a three volume bound set of “Fairchild Research Published Technical Papers” assembled by Bruce Deal in 1988 (copy in the CHM Fairchild collection).