Fairchild 1024-bit SAM multi-chip memory plane uses sixteen 64-bit PMOS Static RAM chips (1968)
Credit: Fairchild Camera & Instrument Corporation.

John Schmidt designed a 64-bit MOS p-channel Static RAM at Fairchild in 1964. Fairchild’s 1968 SAM (Semiconductor Active Memory) program for Burroughs assembled sixteen of these chips on ceramic substrates to form 1024-bit hybrid arrays. Monolithic solutions soon overtook this and similar multi-chip projects at Computer Microtechnology, Intel, Motorola, and TI (SMA 2001).

Significant memory cell size reduction is achieved by using dynamic circuitry to refresh stored data. Lee Boysel built a 256-bit dynamic RAM (DRAM) at Fairchild in 1968 and a 1024-bit (1K) device at Four Phase Systems in 1969. Advanced Memory Systems (AMS6001) also offered 1K DRAMs. These designs employed between 4 and 6 transistors per bit. Silicon gate technology (1968 Milestone) combined with a novel three-transistor per bit design by Joel Karp and Bill Regitz allowed Intel to produce the i1103 1K DRAM in half the die area in 1970. At a price of 1 cent/bit, Intel aggressively pursued replacing magnetic core technology for computer main memory. Walter Krolikowski of Cogar described a 1024-bit n-channel DRAM in 1970 but it took IBM’s design on System 370/158 in 1972 to move this higher-speed technology into volume production.

Mostek's Robert Proebsting used ion-implanted resistors to reduce power consumption and die size sufficiently to pack 4K bits (MK4096) into a conventional 16-pin package in 1973. At the 16K level (MK4116) in 1976 Mostek adopted the single transistor memory cell patented by IBM researcher Robert Dennard and design methods described by Karl-Ulrich Stein of Siemens. This approach led to 64K DRAMs from Japanese and US vendors before the end of the decade and large capacity semiconductor memory systems that were as reliable as and more economical than magnetic cores.