John Schmidt designed a 64-bit MOS p-channel Static RAM at Fairchild in 1964. Fairchild's 1968 SAM (Semiconductor Active Memory) program for Burroughs assembled sixteen of these chips on ceramic substrates to form 1024-bit hybrid arrays. Monolithic solutions soon overtook this and similar multi-chip projects at Computer Microtechnology, Intel, Motorola, and TI (SMA 2001).
To reduce chip size Joel Karp of GMe conceived a dynamic clocking scheme that Lee Boysel adapted to build 256-bit dynamic RAMs at Fairchild in 1968 and 1024 and 2048-bit devices at Four Phase Systems in 1969. These and competing DRAMs from Advanced Memory Systems (AMS6001) employed 4 to 6 transistors per bit. Honeywell's Bill Regitz proposed a 3-transistor cell that was implemented by Karp in Intel's p-channel silicon gate process (1968 Milestone). Improvements suggested by Ted Hoff, designed by Bob Abbott and debugged by Bob Reed resulted in the 1103. Offering much faster speed and priced at 1 cent/bit, beginning in 1970 the 1103 quickly replaced magnetic core technology for computer main memory. Walter Krolikowski of Cogar described an even faster n-channel DRAM in 1970. IBM was the first manufacturer to commit to this new process technology on System 370/158 in 1972.
Mostek's Robert Proebsting used ion-implanted resistors to reduce power consumption and die size sufficiently to pack 4K bits (MK4096) into a conventional 16-pin package in 1973. At the 16K level (MK4116) in 1976 Mostek adopted the single transistor memory cell patented by IBM researcher Robert Dennard and design methods described by Karl-Ulrich Stein of Siemens. This approach led to 64K DRAMs from Japanese and US vendors before the end of the decade and large capacity semiconductor memory systems that were as reliable as and more economical than magnetic cores.
Dennard, R. H. "Field-effect transistor memory," U. S. Patent 3,387,286 (Filed July 14, 1967. Issued June 4, 1968).
Regitz, W. and Karp, J. "A three transistor-cell, 1024-bit, 500 ns MOS RAM," Solid-State Circuits Conference. Digest of Technical Papers. 1970 IEEE International, Vol. XIII (Feb 1970) pp. 42-43.
Boysel, L., Chan, W., & Faith, J. "Random access MOS memory packs more bits to the chip," Electronics (February 16, 1970) pp. 109-115.
Krolikowski, W., Brown, W., Dries, R., Foote, R., Lund, D., Plimley, R., Reuter, J. Sandhu, J., Scow, K., Tuttle, J. "A 1024 bit N-channel MOS read-write memory chip," Electron Devices Meeting, 1970 International, Vol. 16 (1970) p. 16
Stein, K.U. and Friedrich, H. "A 1-mil square single-transistor memory cell in n silicon-gate technology," IEEE Journal of Solid-State Circuits, Vol. 8, Issue 5 (Oct 1973) pp. 319-323.
Schroeder, P., Proebsting, R. "A 16K × 1 bit dynamic RAM," Solid-State Circuits Conference. Digest of Technical Papers 1977 IEEE International, Vol. XX (Feb 1977) pp. 12-13.
Finn, Calvin L "All Semiconductor Memory System Includes Read-Only and Read/Write Chips," HP Journal (December, 1972) pp. 22-24
Pugh, E. W., Critchlow, D. L., Henle, R. A., Russell L. A. "Solid State Memory Development in IBM," IBM Journal of Research and Development, Vol. 25, No. 5 (September 1981) pp. 585-602.
Augarten, Stan. "The 1,024-Bit Dynamic RAM - 1103," State Of The Art: A Photographic History of the Integrated Circuit. (New Haven & New York: Ticknor and Fields, 1983) pp.22, see also pp. 50, 56, and 66.
Dennard, R.H. "Evolution of the MOSFET dynamic RAM - A personal view," IEEE Transactions on Electron Devices, Vol. 31, Issue 11 (Nov 1984) pp. 1549-1555.
Moore, Gordon E. "Intel - Memories and the Microprocessor." Daedalus. Journal of the American Academy of Arts & Sciences (Spring 1996).